Hi, In the goal of simulating a shared L1 cache, I would like to modify the source code for the Gem5 cache to create a cache that always misses. What might be a best approach? Should I just try to forward packets between the CPU side and the mem side? Or should I try to somehow clear the valid bit every time a write occurs? (This may be tricky as it might mess up some of the functional and timing access codes in the cache) Or should I try to put every request in the MSHR?
Thanks, Haiyang
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