You can define number of controller via " --mem-channels-<#>" option of
se/fs.py script. If you deep dive se/fs.py script then you can see they
both call configs/common/MemConfig.py class. If you look into config_mem
method then you can see a number of controller can be configured
#========================
mem_ctrls = []
#....
# The default behaviour is to interleave memory channels on 128
# byte granularity, or cache line granularity if larger than 128
# byte. This value is based on the locality seen across a large
# range of workloads.
intlv_size = max(128, system.cache_line_size.value)
# For every range (most systems will only have one), create an
# array of controllers and set their parameters to match their
# address mapping in the case of a DRAM
for r in system.mem_ranges:
for i in xrange(nbr_mem_ctrls):
mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
intlv_bits,
intlv_size)
# Set the number of ranks based on the command-line
# options if it was explicitly set
if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
mem_ctrl.ranks_per_channel = opt_mem_ranks
if opt_elastic_trace_en:
mem_ctrl.latency = '1ns'
print "For elastic trace, over-riding Simple Memory " \
"latency to 1ns."
mem_ctrls.append(mem_ctrl)
#== register all memcontroller to subsystem
subsystem.mem_ctrls = mem_ctrls
/T
On 03/01/2018 04:14 AM, 김성규 wrote:
Hello.
I'm using gem5, and I want to make a system configuration with one
CPU, and 2 memory (controller) objects connected to master port of
memory bus.
(Attached figure may be help)
I could not find how to attach additional memory and assign address to it.
If it is not an excuse, could you let me know an example code closest
to above configuration?
Thank you.
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