Hi, I would suggest having a look at the SVE support that Giacomo Gabrielly posted for review a while back. There is support for SVE load/store structure instructions [1] there that sound very similar to what you want to achieve.
Cheers, Andreas [1] https://gem5-review.googlesource.com/c/public/gem5/+/13524 On 15/11/2018 11:08, 杜东 wrote: > Hi guys, > I am trying to add a new instructions in Gem5 ARM (FS mode) which can > support loading from two memory addresses into two registers. (The memory > addresses are already stored in two system registers). > I want to implement it in the Minor CPU (specifically, HPI mode). > During developing, I met one problem: > > The memory load operation implemented in Minor CPU requires the > instruction to invoke "initiateMemRead(xc, traceData, EA, Mem, > memAccessFlags);" in initiateAcc stage, and invoke "getMem(pkt, Mem, > traceData);" in the completeAcc stage. > The completeAcc will get one packet from pipeline and then read the > data from the packet. > It seems I need to modify the Minor CPU's code for multiple memory > load... > > Any advices about this? > > Thanks a lot! > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
