Hi Kevin, I believe that most of the MCM depends on the CPU code rather than the memory system. The classic memory system maintains a somewhat strict order and it shouldn't alter the order of the requests further. The cache maintains the order or the requests in the MSHR and it should service them in the order it receives them from the core.
O3PCU is loosely based on the Alpha 21264. Initially it implemented a very relaxed memory model but over time it has been made stricter to support architectures with stricter memory models. When you enable the needsTSO flag you enable some of extra ordering constraints, however I can't say for sure this would be enough. For example in the Arm architecture instructions (e.g., barriers) have flags to specify their ordering constraints wrt other instructions. Nikos On 20/05/2019 16:36, Jason Lowe-Power wrote: > Hi Kevin, > > Yes, I believe that's correct. However, I doubt anyone has ever tested > if the stronger MCM works correctly in this case. So you might need to > do some careful testing and/or dig into the code carefully. > > Cheers, > Jason > > On Sat, May 18, 2019 at 1:36 PM Kevin Smith <kevjs7...@gmail.com > <mailto:kevjs7...@gmail.com>> wrote: > > I have a question regarding the memory consistency model (MCM) when > using different ISAs with the classic memory system. > > My understanding is that the design of gem5 mostly decouples the ISA > semantics from the microarchitectural implementation in order to > more easily support multiple ISAs. There is the needsTSO flag > enabled for x86 > (https://github.com/gem5/gem5/blob/master/src/cpu/o3/O3CPU.py#L179), > but otherwise all else is the same regardless of ISA selection. > > As a result, for example, if I was to use the Alpha ISA but also > enable the needsTSO flag, I would essentially be using an Alpha > simulator but with x86 MCM semantics, correct? I.e. I would have > total store ordering even though I am using Alpha? > > Thanks for any info/help! > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org <mailto:gem5-users@gem5.org> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
