Hi all,
We need to implement an instruction set simulator for a very simple CPU, and I
think gem5's SE mode looks promising to me.
Our ISA is a subset of MIPS-I, except that SW and LW instructions have their
original opcodes changed. To begin with, I removed all the unused instructions
in src/arch/mips/isa, and put SW and LW to the right place in decoder.isa.
Then, I used our own cross compiler to compile a benchmark into an ELF, and
simulate it with gem5's SE mode. I also used remote gdb to single step the
ELF's assembly instructions. Then my SW and LW exhibited some inconsistent
unexpected behaviors. It means something is not right.
I used to investigate QEMU's User Space Emulation mode, which is just like
gem5's SE mode. I did the same change to QEMU's MIPS ISA, and used remote gdb
on it as well. Interestingly, the SW and LW behaved the same as in gem5. Hence,
I think my ISA implementation may be right. It's just some other parts made it
wrong.
Unlike QEMU, gem5's source code is highly modular. After looking at it, I think
gem5 may be a better solution for our purpose than QEMU.
So, my question is, how to implement a simple MIPS-I subset instruction set
simulator from scratch? The AtomicSimpleCPU model is good enough, all we need
is just to see how the ISA manipulates the registers and memory.
Thank you very much in advance.
Regards,
Libo
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