Hi everyone,
This is an update on the issue I posted earlier.
It seems that when using SMT with x86, the se.py configuration file defines
the connections of PIO and interrupt ports to the memory bus only for the
first SMT core. I got around this issue by modifying se.py as follows (I
added the last three lines in the code below), assuming there are two SMT
cores in total:
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts[0].pio = ruby_port.master
system.cpu[i].interrupts[0].int_master = ruby_port.slave
system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].interrupts[1].pio = ruby_port.master
system.cpu[i].interrupts[1].int_master = ruby_port.slave
system.cpu[i].interrupts[1].int_slave = ruby_port.master
Adding such connections for the classic caches seems to be harder, so I did
it for the ruby model.
I then ran gem5 and got this new error:
gem5.opt: build/X86/cpu/o3/rename_map.cc:82: SimpleRenameMap::RenameInfo
SimpleRenameMap::rename(const RegId&): Assertion `prev_reg->isZeroReg()'
failed.
This problem of the zero register has been discussed a long time ago in the
gem5 mailing list:
https://www.mail-archive.com/gem5-users@gem5.org/msg04271.html
It seems that a patch was suggested for it. Since this zero register issue
still persists, I wonder if it has been reviewed/applied.
Thanks,
Hossein
On Wed, Oct 30, 2019 at 3:42 PM Hossein Golestani <hosse...@umich.edu>
wrote:
> Hello,
>
> When I use an O3 SMT core with the x86 ISA in gem5 SE mode, I get the
> following error:
> panic: panic condition !intMasterPort.isConnected() occurred: Int port not
> connected to anything!
>
> The command I'm using is:
> $GEM5/build/X86/gem5.opt $GEM5/configs/example/se.py --cmd="./test;./test"
> --cpu-type=DerivO3CPU --smt --caches --l2cache
>
> (When I use only one workload, i.e., --cmd="./test", there will be no
> error.)
>
> The only occurrence of the interrupt port in se.py is the following:
> if buildEnv['TARGET_ISA'] == 'x86':
> system.cpu[i].interrupts[0].pio = ruby_port.master
> system.cpu[i].interrupts[0].int_master = ruby_port.slave
> system.cpu[i].interrupts[0].int_slave = ruby_port.master
>
> So, I also used the ruby memory model (--ruby). But I still get the same
> error.
>
> I would really appreciate any help on this issue.
>
> Thanks,
> Hossein
>
>
>
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