Hi all, I have seen that multicore support for RISC-V ISA was implemented by some researchers from Cornell University. I ran into these <http://www.csl.cornell.edu/~cbatten/pdfs/ta-gem5-riscv-slides-carrv2018.pdf> slides. In one of the slides, they try to pull some changes ( https://gem5.googlesource.com/public/gem5 refs/changes/26/9626/4 and https://gem5.googlesource.com/public/gem5 refs/changes/44/9644/3) from the repository which are not available anymore. Are these changes merged in upstream gem5?
Best, Muhammet
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
