Hello everyone, I'm facing an issue regarding using the RISC-V ISA with the DerivO3CPU model. Apparently, some RISC-V instructions are incorrectly detected as a branch. Here's a piece of debugging output: 5682918000: system.switch_cpus.fetch: [tid:0] Instruction PC 0x10586 (0) created [sn:1]. 5682918000: system.switch_cpus.fetch: [tid:0] Instruction is: *c_fsd* fa5, 72(a5) 5682918000: system.switch_cpus.fetch: [tid:0] Fetch queue entry created (1/32). 5682918000: system.switch_cpus.fetch: *Branch detected* with PC = (0x10586=>0x10588).(0=>1) 5682918000: system.switch_cpus.fetch: [tid:0] *Done fetching*, predicted branch instruction encountered.
c_fsd is a floating-point store rather than a branch. I observed such an issue for other non-branch instructions, including c_ld, c_sd, and c_mv. As you can see, this problem seems to have to do with RISC-V compressed instructions, as also suggested in a previous post (link <https://www.mail-archive.com/gem5-users@gem5.org/msg15576.html>). This problem causes inaccuracies in performance modeling of the OoO core, that is, since branch prediction needs to be performed at the fetch stage, no other instruction (as far as fetch bandwidth allows) is fetched after the wrong branches. Looking a bit in the code of the DefaultFetch<Impl>::fetch function in src/cpu/o3/fetch_impl.hh, it seems thisPC.branching() returns true for the instructions mentioned above. For the RISC-V ISA, this function is implemented in src/arc/riscv/types.hh. Before trying to solve this problem on my own, I just wanted to report it here to see if anyone can help. I will send a follow-up email if I make progress on this. By the way, I'm using the commit c4724cac6 of gem5 (3 months old as of today). Thanks, Hossein
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