Hi Anuj, Method 1: If you already know the address range, for classic cache model, in the “src/mem/cache/base.cc” file see the recvTimingReq function. When the address lies in your desired address range turn the NonCacheable request flag high for that block. You can find information about this flag in “src/mem/request.hh” or “src/mem/packer.hh” file.
Method 2(classic cache model): Search for allocateBlock function call in “src/mem/cache/base.cc” and then do not fill/allocate the desired address range blocks to be filled in cache. Please note that you may want to change the timing of access and response of those blocks depending on whether you want to add cache access timing to that block access or not On Fri, Jun 26, 2020 at 4:19 AM Anuj Falcon via gem5-users < gem5-users@gem5.org> wrote: > With the caches on, is there a way to define certain memory ranges for the > CPU to directly access memory (Not through the L1 or L2) ? Can somebody > provide any example on how to do that ? > > > -- > > --------------------------------------------------------------------------------- > J ANUJ > > --------------------------------------------------------------------------------- > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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