Also, in ARM more specifically, you can see miscregs at https://github.com/gem5/gem5/blob/cc3e12b504c20b3bc78db52059d3f4f9b02dfbe8/src/arch/arm/miscregs.hh#L56
Most are what the ARM manuals call "System Registers", but a few others are just convenient ways to implement other ISA features like e.g. MISCREG_LOCKADDR for LLSC. On Wed, Jul 8, 2020 at 4:31 AM Gabe Black via gem5-users <gem5-users@gem5.org> wrote: > > A long time ago when gem5 just supported Alpha, there were three types of > registers, integers, floats, and everything else. The "everything else" were > essentially control registers, or in other words registers which had side > effects from accessing them. They were called "Misc" for miscellaneous since > they were the left overs if you took away the ints and the floats. There are > more types of registers now, but the control registers are still called > "Misc". > > Gabe > > On Tue, Jul 7, 2020 at 2:01 PM Shougang Yuan via gem5-users > <gem5-users@gem5.org> wrote: >> >> Hi, All, >> >> I have one question regarding the miscellaneous register. IN the O3 cpu >> model, it mentioned the miscellaneous register(or misc register) a lot of >> times. So what's the exact meaning of this register? Can anyone give some >> hints? >> >> Best regards. >> Yuan >> _______________________________________________ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
