Hi all, I didn't hear from anybody. So this is just a gentle reminder. It would be helpful if someone can respond. Thanks!
On Tue, 8 Sep, 2020, 12:00 PM Aritra Bagchi, <bagchi95ari...@gmail.com> wrote: > Hi all, > I am using classic cache models in gem5. I have three levels of > caches in the hierarchy: L1-D/I, L2, L3. Whenever there is an L3 miss, the > data is fetched from memory and written to L3 using a latency equals to the > response latency of L3. > After tracing a memory request packet, I have found that the data is then > written to L2, and next to L1-D, and after that it is available at the > cpu_side port of L1-D so that the core can get it. > > Instead of this, if I wanted to forward the data fetched from the > main memory directly to the requesting core, and let these writes happen > independently so that the core doesn't have to unnecessarily wait for its > data, what do I need to do? I want suggestions to start. Can it be done? > What changes need to be made, and where? Can anyone help me with this? > > Thanks and regards, > > Aritra Bagchi > Research Scholar, CSE > Indian Institute of Technology Delhi > >
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
