Hi all.
I hope everyone is doing good. I recently started working with gem5
simulator. I am trying to do some modification to the page table walker
(pagetable_walker). My problem is that booting linux under full system
emulation is very slow. It takes nearly 30 to 40 minutes to boot. I am
using AtomicSimpleCPU. I just want to know if this is the normal case for
this cpu type.
I also tried with X86KvmCPU and I used the following command,
$gem5_dir/build/X86/gem5.opt $gem5_config_dir/example/fs.py --kernel
$linux_dir/vmlinux --disk-image $cur_dir/qemu-image.img --caches --l2cache
--cpu-type X86KvmCPU --fast-forward 1000000000
This was faster than atomic simple cpu but the problem here is that all
stats are cleared up at the end. I shall attach an example stat file with
this email. In the stat file attached, you may see all the tlb stats
cleared. I wish to know the reason why stats are cleared in examples/fs.py
I just want to know if there is any way to fasten boot up with an atomic
simple cpu or is this normal? My work is basically to change the kernel,
compile it, run under gem5 and check the stats.
Any kind of suggestions are most appreciated.
Thank you.
--
Regards,
Krishnan.
---------- Begin Simulation Statistics ----------
final_tick 265601000000000000
# Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
host_inst_rate 178253002 #
Simulator instruction rate (inst/s)
host_mem_usage 2818636 #
Number of bytes of host memory used
host_op_rate 207029784 #
Simulator op (including micro ops) rate (op/s)
host_seconds 41.12 #
Real time elapsed on the host
host_tick_rate 6459743431304160
# Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 7329030227 #
Number of instructions simulated
sim_ops 8512227813 #
Number of ops (including micro ops) simulated
sim_seconds 265598.640391 #
Number of seconds simulated
sim_ticks 265598640390735008
# Number of ticks simulated
system.cpu.committedInsts 0 #
Number of instructions committed
system.cpu.committedOps 0 #
Number of ops (including micro ops) committed
system.cpu.dtb.rdAccesses 0 #
TLB accesses on read requests
system.cpu.dtb.rdMisses 0 #
TLB misses on read requests
system.cpu.dtb.wrAccesses 0 #
TLB accesses on write requests
system.cpu.dtb.wrMisses 0 #
TLB misses on write requests
system.cpu.idle_fraction 0 #
Percentage of idle cycles
system.cpu.itb.rdAccesses 0 #
TLB accesses on read requests
system.cpu.itb.rdMisses 0 #
TLB misses on read requests
system.cpu.itb.wrAccesses 0 #
TLB accesses on write requests
system.cpu.itb.wrMisses 0 #
TLB misses on write requests
system.cpu.kern.inst.arm 0 #
number of arm instructions executed
system.cpu.kern.inst.quiesce 0 #
number of quiesce instructions executed
system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
system.cpu.numCycles 0 #
number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.num_busy_cycles 0 #
Number of busy cycles
system.cpu.num_conditional_control_insts 0 #
number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 0 #
Number of float alu accesses
system.cpu.num_fp_insts 0 #
number of float instructions
system.cpu.num_fp_register_reads 0 #
number of times the floating registers were read
system.cpu.num_fp_register_writes 0 #
number of times the floating registers were written
system.cpu.num_func_calls 0 #
number of times a function call or return occured
system.cpu.num_idle_cycles 0 #
Number of idle cycles
system.cpu.num_int_alu_accesses 0 #
Number of integer alu accesses
system.cpu.num_int_insts 0 #
number of integer instructions
system.cpu.num_int_register_reads 0 #
number of times the integer registers were read
system.cpu.num_int_register_writes 0 #
number of times the integer registers were written
system.cpu.num_load_insts 0 #
Number of load instructions
system.cpu.num_mem_refs 0 #
number of memory refs
system.cpu.num_store_insts 0 #
Number of store instructions
system.cpu.num_vec_alu_accesses 0 #
Number of vector alu accesses
system.cpu.num_vec_insts 0 #
number of vector instructions
system.cpu.num_vec_register_reads 0 #
number of times the vector registers were read
system.cpu.num_vec_register_writes 0 #
number of times the vector registers were written
system.cpu.op_class::No_OpClass 0 #
Class of executed instruction
system.cpu.op_class::IntAlu 0 #
Class of executed instruction
system.cpu.op_class::IntMult 0 #
Class of executed instruction
system.cpu.op_class::IntDiv 0 #
Class of executed instruction
system.cpu.op_class::FloatAdd 0 #
Class of executed instruction
system.cpu.op_class::FloatCmp 0 #
Class of executed instruction
system.cpu.op_class::FloatCvt 0 #
Class of executed instruction
system.cpu.op_class::FloatMult 0 #
Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 #
Class of executed instruction
system.cpu.op_class::FloatDiv 0 #
Class of executed instruction
system.cpu.op_class::FloatMisc 0 #
Class of executed instruction
system.cpu.op_class::FloatSqrt 0 #
Class of executed instruction
system.cpu.op_class::SimdAdd 0 #
Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 #
Class of executed instruction
system.cpu.op_class::SimdAlu 0 #
Class of executed instruction
system.cpu.op_class::SimdCmp 0 #
Class of executed instruction
system.cpu.op_class::SimdCvt 0 #
Class of executed instruction
system.cpu.op_class::SimdMisc 0 #
Class of executed instruction
system.cpu.op_class::SimdMult 0 #
Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 #
Class of executed instruction
system.cpu.op_class::SimdShift 0 #
Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 #
Class of executed instruction
system.cpu.op_class::SimdDiv 0 #
Class of executed instruction
system.cpu.op_class::SimdSqrt 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 #
Class of executed instruction
system.cpu.op_class::SimdReduceAdd 0 #
Class of executed instruction
system.cpu.op_class::SimdReduceAlu 0 #
Class of executed instruction
system.cpu.op_class::SimdReduceCmp 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatReduceAdd 0 #
Class of executed instruction
system.cpu.op_class::SimdFloatReduceCmp 0 #
Class of executed instruction
system.cpu.op_class::SimdAes 0 #
Class of executed instruction
system.cpu.op_class::SimdAesMix 0 #
Class of executed instruction
system.cpu.op_class::SimdSha1Hash 0 #
Class of executed instruction
system.cpu.op_class::SimdSha1Hash2 0 #
Class of executed instruction
system.cpu.op_class::SimdSha256Hash 0 #
Class of executed instruction
system.cpu.op_class::SimdSha256Hash2 0 #
Class of executed instruction
system.cpu.op_class::SimdShaSigma2 0 #
Class of executed instruction
system.cpu.op_class::SimdShaSigma3 0 #
Class of executed instruction
system.cpu.op_class::SimdPredAlu 0 #
Class of executed instruction
system.cpu.op_class::MemRead 0 #
Class of executed instruction
system.cpu.op_class::MemWrite 0 #
Class of executed instruction
system.cpu.op_class::FloatMemRead 0 #
Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 #
Class of executed instruction
system.cpu.op_class::IprAccess 0 #
Class of executed instruction
system.cpu.op_class::InstPrefetch 0 #
Class of executed instruction
system.cpu.op_class::total 0 #
Class of executed instruction
system.membus.snoop_filter.hit_multi_requests 0
# Number of requests hitting in the snoop filter with multiple (>1) holders of
the requested data.
system.membus.snoop_filter.hit_multi_snoops 0
# Number of snoops hitting in the snoop filter with multiple (>1) holders of
the requested data.
system.membus.snoop_filter.hit_single_requests 0
# Number of requests hitting in the snoop filter with a single holder of the
requested data.
system.membus.snoop_filter.hit_single_snoops 0
# Number of snoops hitting in the snoop filter with a single holder of the
requested data.
system.membus.snoop_filter.tot_requests 0 #
Total number of requests made to the snoop filter.
system.membus.snoop_filter.tot_snoops 0 #
Total number of snoops made to the snoop filter.
system.pc.south_bridge.ide.disks.dma_read_bytes 8654848
# Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks.dma_read_full_pages 2113
# Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks.dma_read_txs 2113
# Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks.dma_write_bytes 29265920
# Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks.dma_write_full_pages 7145
# Number of full page size DMA writes.
system.pc.south_bridge.ide.disks.dma_write_txs 7145
# Number of DMA write transactions.
system.switch_cpus.committedInsts 6329030226 #
Number of instructions committed
system.switch_cpus.dtb.rdAccesses 0 #
TLB accesses on read requests
system.switch_cpus.dtb.rdMisses 0 #
TLB misses on read requests
system.switch_cpus.dtb.wrAccesses 0 #
TLB accesses on write requests
system.switch_cpus.dtb.wrMisses 0 #
TLB misses on write requests
system.switch_cpus.itb.rdAccesses 0 #
TLB accesses on read requests
system.switch_cpus.itb.rdMisses 0 #
TLB misses on read requests
system.switch_cpus.itb.wrAccesses 0 #
TLB accesses on write requests
system.switch_cpus.itb.wrMisses 0 #
TLB misses on write requests
system.switch_cpus.kern.inst.arm 0 #
number of arm instructions executed
system.switch_cpus.kern.inst.quiesce 0 #
number of quiesce instructions executed
system.switch_cpus.numCoalescedMMIO 0 #
number of coalesced memory mapped IO requests
system.switch_cpus.numCycles 1310483775853 #
number of cpu cycles simulated
system.switch_cpus.numExitSignal 689887 #
exits due to signal delivery
system.switch_cpus.numHalt 653143 #
number of VM exits due to wait for interrupt instructions
system.switch_cpus.numHypercalls 0 #
number of hypercalls
system.switch_cpus.numIO 94523 #
number of VM exits due to legacy IO
system.switch_cpus.numInterrupts 659549 #
number of interrupts delivered
system.switch_cpus.numMMIO 660001 #
number of VM exits due to memory mapped IO
system.switch_cpus.numVMExits 2100797 #
total number of KVM exits
system.switch_cpus.numVMHalfEntries 0 #
number of KVM entries to finalize pending operations
system.switch_cpus.numWorkItemsCompleted 0 #
number of work items this cpu completed
system.switch_cpus.numWorkItemsStarted 0 #
number of work items this cpu started
system.tol2bus.snoop_filter.hit_multi_requests 0
# Number of requests hitting in the snoop filter with multiple (>1) holders
of the requested data.
system.tol2bus.snoop_filter.hit_multi_snoops 0
# Number of snoops hitting in the snoop filter with multiple (>1) holders of
the requested data.
system.tol2bus.snoop_filter.hit_single_requests 0
# Number of requests hitting in the snoop filter with a single holder of the
requested data.
system.tol2bus.snoop_filter.hit_single_snoops 0
# Number of snoops hitting in the snoop filter with a single holder of the
requested data.
system.tol2bus.snoop_filter.tot_requests 0 #
Total number of requests made to the snoop filter.
system.tol2bus.snoop_filter.tot_snoops 0 #
Total number of snoops made to the snoop filter.
system.bridge.power_state.pwrStateResidencyTicks::UNDEFINED 265601000000000000
# Cumulative time (in ticks) in various power states
system.voltage_domain.voltage 1 #
Voltage in Volts
system.iocache.blocked_cycles::no_mshrs 0 #
number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 #
number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.iocache.blocked::no_targets 0 #
number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan
# average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan
# average number of cycles each access was blocked
system.iocache.replacements 0 #
number of replacements
system.iocache.power_state.pwrStateResidencyTicks::UNDEFINED 265601000000000000
# Cumulative time (in ticks) in various power states
system.iocache.tags.tagsinuse 0 #
Cycle average of tags in use
system.iocache.tags.total_refs 0 #
Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 #
Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan #
Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses 0 #
Number of tag accesses
system.iocache.tags.data_accesses 0 #
Number of data accesses
system.iocache.tags.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.membus.trans_dist::ReadReq 195040 #
Transaction distribution
system.membus.trans_dist::ReadResp 195040 #
Transaction distribution
system.membus.trans_dist::WriteReq 1172391 #
Transaction distribution
system.membus.trans_dist::WriteResp 1172391 #
Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave
30762 # Packet count per connected master and
slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 30762
# Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.mem_ctrls.port
1195052 # Packet count per connected master and slave
(bytes)
system.membus.pkt_count_system.iocache.mem_side::total 1195052
# Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2.mem_side::system.bridge.slave 189812
# Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2.mem_side::system.cpu.interrupts.pio
1319236 # Packet count per connected master and slave
(bytes)
system.membus.pkt_count_system.l2.mem_side::total 1509048
# Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2734862 #
Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave
61524 # Cumulative packet size per connected
master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 61524
# Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.mem_ctrls.port
37960880 # Cumulative packet size per connected master
and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 37960880
# Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2.mem_side::system.bridge.slave 100933
# Cumulative packet size per connected master and slave
(bytes)
system.membus.pkt_size_system.l2.mem_side::system.cpu.interrupts.pio
2638472 # Cumulative packet size per connected master and
slave (bytes)
system.membus.pkt_size_system.l2.mem_side::total 2739405
# Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 40761809 #
Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 #
Total snoops (count)
system.membus.snoopTraffic 0 #
Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 0 #
Request fanout histogram
system.membus.snoop_fanout::mean nan #
Request fanout histogram
system.membus.snoop_fanout::stdev nan #
Request fanout histogram
system.membus.snoop_fanout::underflows 0 #
Request fanout histogram
system.membus.snoop_fanout::0 0 #
Request fanout histogram
system.membus.snoop_fanout::1 0 #
Request fanout histogram
system.membus.snoop_fanout::2 0 #
Request fanout histogram
system.membus.snoop_fanout::overflows 0 #
Request fanout histogram
system.membus.snoop_fanout::min_value 0 #
Request fanout histogram
system.membus.snoop_fanout::max_value 0 #
Request fanout histogram
system.membus.snoop_fanout::total 0 #
Request fanout histogram
system.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 265601000000000000
# Cumulative time (in ticks) in various power states
system.tol2bus.trans_dist::ReadReq 54794 #
Transaction distribution
system.tol2bus.trans_dist::ReadResp 54794 #
Transaction distribution
system.tol2bus.trans_dist::WriteReq 699730 #
Transaction distribution
system.tol2bus.trans_dist::WriteResp 699730 #
Transaction distribution
system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side
1509048 # Packet count per connected master and slave
(bytes)
system.tol2bus.pkt_count::total 1509048 #
Packet count per connected master and slave (bytes)
system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side
2739405 # Cumulative packet size per connected master and
slave (bytes)
system.tol2bus.pkt_size::total 2739405 #
Cumulative packet size per connected master and slave (bytes)
system.tol2bus.snoops 0 #
Total snoops (count)
system.tol2bus.snoopTraffic 0 #
Total snoop traffic (bytes)
system.tol2bus.snoop_fanout::samples 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::mean nan #
Request fanout histogram
system.tol2bus.snoop_fanout::stdev nan #
Request fanout histogram
system.tol2bus.snoop_fanout::underflows 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::0 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::1 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::2 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::3 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::4 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::overflows 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::min_value 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::max_value 0 #
Request fanout histogram
system.tol2bus.snoop_fanout::total 0 #
Request fanout histogram
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 265601000000000000
# Cumulative time (in ticks) in various power states
system.clk_domain.clock 1000 #
Clock period in ticks
system.apicbridge.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.fake_com_4.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.fake_com_2.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.fake_com_3.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.io_apic.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.pic1.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.pic2.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.dma1.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.speaker.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.keyboard.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.ide.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.pit.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.south_bridge.cmos.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.i_dont_exist2.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.i_dont_exist1.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.com_1.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.fake_floppy.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.behind_pci.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.pc.pci_host.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.l2.blocked_cycles::no_mshrs 0 #
number of cycles access was blocked
system.l2.blocked_cycles::no_targets 0 #
number of cycles access was blocked
system.l2.blocked::no_mshrs 0 #
number of cycles access was blocked
system.l2.blocked::no_targets 0 #
number of cycles access was blocked
system.l2.avg_blocked_cycles::no_mshrs nan #
average number of cycles each access was blocked
system.l2.avg_blocked_cycles::no_targets nan #
average number of cycles each access was blocked
system.l2.replacements 0 #
number of replacements
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 265601000000000000
# Cumulative time (in ticks) in various power states
system.l2.tags.tagsinuse 0 #
Cycle average of tags in use
system.l2.tags.total_refs 0 #
Total number of references to valid blocks.
system.l2.tags.sampled_refs 0 #
Sample count of references to valid blocks.
system.l2.tags.avg_refs nan #
Average number of references to valid blocks.
system.l2.tags.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.l2.tags.tag_accesses 0 #
Number of tag accesses
system.l2.tags.data_accesses 0 #
Number of data accesses
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265601000000000000
# Cumulative time (in ticks) in various power states
system.cpu_voltage_domain.voltage 1 #
Voltage in Volts
system.mem_ctrls.bytes_read::.pc.south_bridge.ide 8694960
# Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 8694960 #
Number of bytes read from this memory
system.mem_ctrls.bytes_written::.pc.south_bridge.ide 29265920
# Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 29265920 #
Number of bytes written to this memory
system.mem_ctrls.num_reads::.pc.south_bridge.ide 140246
# Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 140246 #
Number of read requests responded to by this memory
system.mem_ctrls.num_writes::.pc.south_bridge.ide 457280
# Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 457280 #
Number of write requests responded to by this memory
system.mem_ctrls.bw_read::.pc.south_bridge.ide 33
# Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 33 #
Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::.pc.south_bridge.ide 110
# Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 110 #
Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::.pc.south_bridge.ide 143
# Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 143 #
Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.priorityMinLatency 0.000000000000 #
per QoS priority minimum request to response latency (s)
system.mem_ctrls.priorityMaxLatency 0.000000000000 #
per QoS priority maximum request to response latency (s)
system.mem_ctrls.numReadWriteTurnArounds 0 #
Number of turnarounds from READ to WRITE
system.mem_ctrls.numWriteReadTurnArounds 0 #
Number of turnarounds from WRITE to READ
system.mem_ctrls.numStayReadState 0 #
Number of times bus staying in READ state
system.mem_ctrls.numStayWriteState 0 #
Number of times bus staying in WRITE state
system.mem_ctrls.readReqs 0 #
Number of read requests accepted
system.mem_ctrls.writeReqs 0 #
Number of write requests accepted
system.mem_ctrls.readBursts 0 #
Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 0 #
Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.servicedByWrQ 0 #
Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 0 #
Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 #
Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 #
Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 0 #
Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 #
Per bank write bursts
system.mem_ctrls.avgRdQLen 0.00 #
Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 0.00 #
Average write queue length when enqueuing
system.mem_ctrls.totQLat 0 #
Total ticks spent queuing
system.mem_ctrls.totBusLat 0 #
Total ticks spent in databus transfers
system.mem_ctrls.totMemAccLat 0 #
Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.avgQLat nan #
Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat nan #
Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat nan #
Average memory access latency per DRAM burst
system.mem_ctrls.numRdRetry 0 #
Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 #
Number of times write queue was full causing retry
system.mem_ctrls.readRowHits 0 #
Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 0 #
Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate nan #
Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate nan #
Row buffer hit rate for writes
system.mem_ctrls.readPktSize::0 0 #
Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 #
Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 #
Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 #
Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 #
Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 #
Read request sizes (log2)
system.mem_ctrls.readPktSize::6 0 #
Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 #
Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 #
Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 #
Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 #
Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 #
Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 #
Write request sizes (log2)
system.mem_ctrls.writePktSize::6 0 #
Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 #
What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 #
What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 #
What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 #
What write queue length does an incoming req see
system.mem_ctrls.bytesReadDRAM 0 #
Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 0 #
Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 0 #
Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 0 #
Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 0 #
Total written bytes from the system interface side
system.mem_ctrls.avgRdBW 0.00 #
Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 0.00 #
Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 0.00 #
Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 0.00 #
Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 #
Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 0.00 #
Data bus utilization in percentage
system.mem_ctrls.busUtilRead 0.00 #
Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.00 #
Data bus utilization in percentage for writes
system.mem_ctrls.totGap 0 #
Total gap between requests
system.mem_ctrls.avgGap nan #
Average gap between requests
system.mem_ctrls.pageHitRate nan #
Row buffer hit rate, read and write combined
system.mem_ctrls.rank1.actEnergy 0 #
Energy for activate commands per rank (pJ)
system.mem_ctrls.rank1.preEnergy 0 #
Energy for precharge commands per rank (pJ)
system.mem_ctrls.rank1.readEnergy 0 #
Energy for read commands per rank (pJ)
system.mem_ctrls.rank1.writeEnergy 0 #
Energy for write commands per rank (pJ)
system.mem_ctrls.rank1.refreshEnergy 0 #
Energy for refresh commands per rank (pJ)
system.mem_ctrls.rank1.actBackEnergy 0 #
Energy for active background per rank (pJ)
system.mem_ctrls.rank1.preBackEnergy 101989877910042240
# Energy for precharge background per rank (pJ)
system.mem_ctrls.rank1.actPowerDownEnergy 0 #
Energy for active power-down per rank (pJ)
system.mem_ctrls.rank1.prePowerDownEnergy 0 #
Energy for precharge power-down per rank (pJ)
system.mem_ctrls.rank1.selfRefreshEnergy 0 #
Energy for self refresh per rank (pJ)
system.mem_ctrls.rank1.totalEnergy 101989877910042240
# Total energy per rank (pJ)
system.mem_ctrls.rank1.averagePower 384 #
Core power per rank (mW)
system.mem_ctrls.rank1.totalIdleTime 0 #
Total Idle time Per DRAM Rank
system.mem_ctrls.rank1.memoryStateTime::IDLE 265601000000000000
# Time in different power states
system.mem_ctrls.rank1.memoryStateTime::REF 0
# Time in different power states
system.mem_ctrls.rank1.memoryStateTime::SREF 0
# Time in different power states
system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0
# Time in different power states
system.mem_ctrls.rank1.memoryStateTime::ACT 0
# Time in different power states
system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0
# Time in different power states
system.mem_ctrls.rank0.actEnergy 0 #
Energy for activate commands per rank (pJ)
system.mem_ctrls.rank0.preEnergy 0 #
Energy for precharge commands per rank (pJ)
system.mem_ctrls.rank0.readEnergy 0 #
Energy for read commands per rank (pJ)
system.mem_ctrls.rank0.writeEnergy 0 #
Energy for write commands per rank (pJ)
system.mem_ctrls.rank0.refreshEnergy 0 #
Energy for refresh commands per rank (pJ)
system.mem_ctrls.rank0.actBackEnergy 0 #
Energy for active background per rank (pJ)
system.mem_ctrls.rank0.preBackEnergy 101989877910042240
# Energy for precharge background per rank (pJ)
system.mem_ctrls.rank0.actPowerDownEnergy 0 #
Energy for active power-down per rank (pJ)
system.mem_ctrls.rank0.prePowerDownEnergy 0 #
Energy for precharge power-down per rank (pJ)
system.mem_ctrls.rank0.selfRefreshEnergy 0 #
Energy for self refresh per rank (pJ)
system.mem_ctrls.rank0.totalEnergy 101989877910042240
# Total energy per rank (pJ)
system.mem_ctrls.rank0.averagePower 384 #
Core power per rank (mW)
system.mem_ctrls.rank0.totalIdleTime 0 #
Total Idle time Per DRAM Rank
system.mem_ctrls.rank0.memoryStateTime::IDLE 265601000000000000
# Time in different power states
system.mem_ctrls.rank0.memoryStateTime::REF 0
# Time in different power states
system.mem_ctrls.rank0.memoryStateTime::SREF 0
# Time in different power states
system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0
# Time in different power states
system.mem_ctrls.rank0.memoryStateTime::ACT 0
# Time in different power states
system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0
# Time in different power states
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.iobus.trans_dist::ReadReq 195013 #
Transaction distribution
system.iobus.trans_dist::ReadResp 195013 #
Transaction distribution
system.iobus.trans_dist::WriteReq 512800 #
Transaction distribution
system.iobus.trans_dist::WriteResp 512800 #
Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio
74828 # Packet count per connected master and slave
(bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio
26 # Packet count per connected master and
slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio
14 # Packet count per connected master and slave
(bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio
2 # Packet count per connected master and slave
(bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio
766 # Packet count per connected master and
slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 114176
# Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 189812
# Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side
1195052 # Packet count per connected master and slave
(bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 1195052
# Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave
30762 # Packet count per connected master and
slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total
30762 # Packet count per connected master and slave
(bytes)
system.iobus.pkt_count::total 1415626 #
Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio
42292 # Cumulative packet size per connected master and
slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio
13 # Cumulative packet size per connected
master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio
7 # Cumulative packet size per connected master
and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio
1 # Cumulative packet size per connected master
and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio
1532 # Cumulative packet size per connected master
and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 57088
# Cumulative packet size per connected master and slave
(bytes)
system.iobus.pkt_size_system.bridge.master::total 100933
# Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side
37960880 # Cumulative packet size per connected master
and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 37960880
# Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave
61524 # Cumulative packet size per connected
master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total
61524 # Cumulative packet size per connected master and
slave (bytes)
system.iobus.pkt_size::total 38123337 #
Cumulative packet size per connected master and slave (bytes)
system.iobus.power_state.pwrStateResidencyTicks::UNDEFINED 265601000000000000
# Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 #
Clock period in ticks
system.cpu.icache.demand_hits::.cpu.inst 1265595907 #
number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1265595907 #
number of demand (read+write) hits
system.cpu.icache.overall_hits::.cpu.inst 1265595907 #
number of overall hits
system.cpu.icache.overall_hits::total 1265595907 #
number of overall hits
system.cpu.icache.demand_misses::.cpu.inst 6869141 #
number of demand (read+write) misses
system.cpu.icache.demand_misses::total 6869141 #
number of demand (read+write) misses
system.cpu.icache.overall_misses::.cpu.inst 6869141
# number of overall misses
system.cpu.icache.overall_misses::total 6869141 #
number of overall misses
system.cpu.icache.demand_accesses::.cpu.inst 1272465048
# number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1272465048 #
number of demand (read+write) accesses
system.cpu.icache.overall_accesses::.cpu.inst 1272465048
# number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1272465048 #
number of overall (read+write) accesses
system.cpu.icache.demand_miss_rate::.cpu.inst 0.005398
# miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.005398 #
miss rate for demand accesses
system.cpu.icache.overall_miss_rate::.cpu.inst 0.005398
# miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.005398 #
miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan
# average number of cycles each access was blocked
system.cpu.icache.writebacks::.writebacks 6868517 #
number of writebacks
system.cpu.icache.writebacks::total 6868517 #
number of writebacks
system.cpu.icache.replacements 6868517 #
number of replacements
system.cpu.icache.ReadReq_hits::.cpu.inst 1265595907 #
number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1265595907 #
number of ReadReq hits
system.cpu.icache.ReadReq_misses::.cpu.inst 6869141
# number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 6869141 #
number of ReadReq misses
system.cpu.icache.ReadReq_accesses::.cpu.inst 1272465048
# number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1272465048 #
number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.005398
# miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005398 #
miss rate for ReadReq accesses
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.icache.tags.tagsinuse 0.004540 #
Cycle average of tags in use
system.cpu.icache.tags.total_refs 1272465048 #
Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6869141 #
Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 185.243693 #
Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::.cpu.inst 0.004540
# Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::.cpu.inst 0.000009
# Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.000009 #
Average percentage of cache occupancy
system.cpu.icache.tags.tag_accesses 2551799237 #
Number of tag accesses
system.cpu.icache.tags.data_accesses 2551799237 #
Number of data accesses
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.interrupts.clk_domain.clock 8000 #
Clock period in ticks
system.cpu.itb_walker_cache.demand_hits::.cpu.itb.walker 1851120
# number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 1851120
# number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::.cpu.itb.walker 1851120
# number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 1851120
# number of overall hits
system.cpu.itb_walker_cache.demand_misses::.cpu.itb.walker 287907
# number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 287907
# number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::.cpu.itb.walker 287907
# number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 287907
# number of overall misses
system.cpu.itb_walker_cache.demand_accesses::.cpu.itb.walker 2139027
# number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 2139027
# number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::.cpu.itb.walker 2139027
# number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 2139027
# number of overall (read+write) accesses
system.cpu.itb_walker_cache.demand_miss_rate::.cpu.itb.walker 0.134597
# miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.134597
# miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::.cpu.itb.walker 0.134597
# miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.134597
# miss rate for overall accesses
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0
# number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0
# number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan
# average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan
# average number of cycles each access was blocked
system.cpu.itb_walker_cache.writebacks::.writebacks 57993
# number of writebacks
system.cpu.itb_walker_cache.writebacks::total 57993
# number of writebacks
system.cpu.itb_walker_cache.replacements 284675 #
number of replacements
system.cpu.itb_walker_cache.ReadReq_hits::.cpu.itb.walker 1851118
# number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 1851118
# number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_misses::.cpu.itb.walker 287907
# number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 287907
# number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_accesses::.cpu.itb.walker 2139025
# number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 2139025
# number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_miss_rate::.cpu.itb.walker 0.134597
# miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.134597
# miss rate for ReadReq accesses
system.cpu.itb_walker_cache.WriteReq_hits::.cpu.itb.walker 2
# number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2
# number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_accesses::.cpu.itb.walker 2
# number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2
# number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.itb_walker_cache.tags.tagsinuse 0.000052 #
Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 2139027
# Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 287907
# Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 7.429576 #
Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 0
# Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::.cpu.itb.walker 0.000052
# Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::.cpu.itb.walker 0.000003
# Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.000003
# Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.tag_accesses 4565961
# Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 4565961
# Number of data accesses
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.dtb_walker_cache.demand_hits::.cpu.dtb.walker 6207928
# number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 6207928
# number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::.cpu.dtb.walker 6207928
# number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 6207928
# number of overall hits
system.cpu.dtb_walker_cache.demand_misses::.cpu.dtb.walker 2205548
# number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 2205548
# number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::.cpu.dtb.walker 2205548
# number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 2205548
# number of overall misses
system.cpu.dtb_walker_cache.demand_accesses::.cpu.dtb.walker 8413476
# number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 8413476
# number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::.cpu.dtb.walker 8413476
# number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 8413476
# number of overall (read+write) accesses
system.cpu.dtb_walker_cache.demand_miss_rate::.cpu.dtb.walker 0.262145
# miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.262145
# miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::.cpu.dtb.walker 0.262145
# miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.262145
# miss rate for overall accesses
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0
# number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0
# number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
# average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan
# average number of cycles each access was blocked
system.cpu.dtb_walker_cache.writebacks::.writebacks 524396
# number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 524396
# number of writebacks
system.cpu.dtb_walker_cache.replacements 2194328 #
number of replacements
system.cpu.dtb_walker_cache.ReadReq_hits::.cpu.dtb.walker 6207928
# number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 6207928
# number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_misses::.cpu.dtb.walker 2205548
# number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 2205548
# number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_accesses::.cpu.dtb.walker 8413476
# number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 8413476
# number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_miss_rate::.cpu.dtb.walker 0.262145
# miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.262145
# miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.dtb_walker_cache.tags.tagsinuse 0.000131 #
Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 8413476
# Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 2205548
# Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 3.814687 #
Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 2500
# Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::.cpu.dtb.walker 0.000131
# Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::.cpu.dtb.walker 0.000008
# Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.000008
# Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.tag_accesses 19032500
# Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 19032500
# Number of data accesses
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.dcache.demand_hits::.cpu.data 385200671 #
number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 385200671 #
number of demand (read+write) hits
system.cpu.dcache.overall_hits::.cpu.data 385278498 #
number of overall hits
system.cpu.dcache.overall_hits::total 385278498 #
number of overall hits
system.cpu.dcache.demand_misses::.cpu.data 5389707 #
number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 5389707 #
number of demand (read+write) misses
system.cpu.dcache.overall_misses::.cpu.data 5857494
# number of overall misses
system.cpu.dcache.overall_misses::total 5857494 #
number of overall misses
system.cpu.dcache.demand_accesses::.cpu.data 390590378
# number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 390590378 #
number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::.cpu.data 391135992
# number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 391135992 #
number of overall (read+write) accesses
system.cpu.dcache.demand_miss_rate::.cpu.data 0.013799
# miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.013799 #
miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::.cpu.data 0.014976
# miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.014976 #
miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan
# average number of cycles each access was blocked
system.cpu.dcache.writebacks::.writebacks 3641446 #
number of writebacks
system.cpu.dcache.writebacks::total 3641446 #
number of writebacks
system.cpu.dcache.replacements 5838477 #
number of replacements
system.cpu.dcache.ReadReq_hits::.cpu.data 240917676 #
number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 240917676 #
number of ReadReq hits
system.cpu.dcache.ReadReq_misses::.cpu.data 3695184
# number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 3695184 #
number of ReadReq misses
system.cpu.dcache.ReadReq_accesses::.cpu.data 244612860
# number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 244612860 #
number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.015106
# miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.015106 #
miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_hits::.cpu.data 144282995 #
number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 144282995 #
number of WriteReq hits
system.cpu.dcache.WriteReq_misses::.cpu.data 1694523
# number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1694523 #
number of WriteReq misses
system.cpu.dcache.WriteReq_accesses::.cpu.data 145977518
# number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 145977518 #
number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.011608
# miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.011608
# miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_hits::.cpu.data 77827
# number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 77827 #
number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_misses::.cpu.data 467787
# number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 467787 #
number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_accesses::.cpu.data 545614
# number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 545614
# number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.857359
# miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.857359
# miss rate for SoftPFReq accesses
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.dcache.tags.tagsinuse 0.009096 #
Cycle average of tags in use
system.cpu.dcache.tags.total_refs 391135992 #
Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 5839913 #
Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 66.976339 #
Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 2500 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::.cpu.data 0.009096
# Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::.cpu.data 0.000009
# Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.000009 #
Average percentage of cache occupancy
system.cpu.dcache.tags.tag_accesses 788111897 #
Number of tag accesses
system.cpu.dcache.tags.data_accesses 788111897 #
Number of data accesses
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.cpu.power_state.numTransitions 2478 #
Number of power state transitions
system.cpu.power_state.ticksClkGated::samples 1238
# Distribution of time spent in the clock gated state
system.cpu.power_state.ticksClkGated::mean 914246160.915186
# Distribution of time spent in the clock gated state
system.cpu.power_state.ticksClkGated::stdev 270404797.278106
# Distribution of time spent in the clock gated state
system.cpu.power_state.ticksClkGated::1000-5e+10 1238 100.00%
100.00% # Distribution of time spent in the clock gated state
system.cpu.power_state.ticksClkGated::min_value 285533
# Distribution of time spent in the clock gated state
system.cpu.power_state.ticksClkGated::max_value 996808500
# Distribution of time spent in the clock gated state
system.cpu.power_state.ticksClkGated::total 1238
# Distribution of time spent in the clock gated state
system.cpu.power_state.pwrStateResidencyTicks::ON 1227772517787
# Cumulative time (in ticks) in various power states
system.cpu.power_state.pwrStateResidencyTicks::CLK_GATED 1131836747213
# Cumulative time (in ticks) in various power states
system.cpu.power_state.pwrStateResidencyTicks::OFF 265598640390735008
# Cumulative time (in ticks) in various power states
system.switch_cpus.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.switch_cpus.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED
265601000000000000 # Cumulative time (in ticks) in
various power states
system.switch_cpus.power_state.pwrStateResidencyTicks::OFF 265601000000000000
# Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
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