Hi Leon, In gem5, the caches are PIPT technically. But, you can model the timing of a VIPT cache by changing the latency of your cache. As far as the kernel boot log is concerned, I am not fully sure if "CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache" refers to the actual hardware cache. Even if it is, VIPT and PIPT should be treated in the same way from software's perspective. Following link might be helpful to know what kernel is exactly doing when this message is printed:
https://linux-arm-kernel.infradead.narkive.com/xBwIht4D/about-cachetype-on-armv7 -Ayaz On Sat, Oct 17, 2020 at 12:21 AM Leon Zhao via gem5-users < gem5-users@gem5.org> wrote: > Hi everyone, > I was running the following command in gem5 the other day: > > ......gem5.opt configs/example/fs.py --ruby --cpu-type=O3_ARM_N1 > --script=tests/test-progs/hello/bin/arm/linux/hello > --kernel=/home/hippo/full_system_images/binaries/vmlinux.vexpress_gem5_v1.20170616 > > and I noticed this appeared in the output: > > [ 0.000000] CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), > cr=14c5387d > [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction > cache > > So when it says "PIPT / VIPT nonaliasing data cache", does it mean that on > the level of data cache, there are two different routes (a) PIPT and (b) > VIPT with no aliasing, or are they basically the same thing just with a > difference in names? > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >
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