Hello everyone, I am using gem5 SE mode and investigating memory operation latencies and how virtual memory can affect them in a superscalar processor (DerivO3CPU).
Does the SE mode consider TLB delays, TLB hit and miss, for instance, or this is implemented only in FullSystem mode? I saw in the stats file that there are stats related to itb and dtb, but in my simulations, they are always zero. Is that an expected behavior? Additionally, I was trying to have a better understanding of how TLB works in gem5, so I enabled TLB debug flag and nothing was printed. I am currently using the gem5 20.1.0.2 Risc-V ISA and se.py as the configuration file, so there is nothing special in my configuration file. Any help would be appreciated. ---------------------------------------------------------------------------------------------------------------------------------------------- Francisco Carlos Silva Junior Phd Student at University of Brasilia
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