Hello everyone, I detected an unexpected behavior in the fetch stage of O3CPU. Every time a memory instruction is fetched, it is detected as a branch, as we can see below.
FullO3CPU: Ticking main, FullO3CPU. 203000: system.cpu.fetch: Running stage. 203000: system.cpu.fetch: Attempting to fetch from [tid:0] 203000: system.cpu.fetch: [tid:0] Adding instructions to queue to decode. 203000: global: Requesting bytes 0x051787aa from address 0x104b4 203000: global: Requesting bytes 0x05130000 from address 0x104b8 203000: global: Decoding instruction 0x00000517 at address 0x104b6 203000: global: DynInst: [sn:16] Instruction created. Instcount for system.cpu = 10 203000: system.cpu.fetch: [tid:0] Instruction PC 0x104b6 (0) created [sn:16]. 203000: system.cpu.fetch: [tid:0] Instruction is: auipc a0, 0 203000: system.cpu.fetch: [tid:0] Fetch queue entry created (1/32). 203000: global: Requesting bytes 0x05130000 from address 0x104b8 203000: global: Requesting bytes 0x6582e965 from address 0x104bc 203000: global: Decoding instruction 0xe9650513 at address 0x104ba 203000: global: DynInst: [sn:17] Instruction created. Instcount for system.cpu = 11 203000: system.cpu.fetch: [tid:0] Instruction PC 0x104ba (0) created [sn:17]. 203000: system.cpu.fetch: [tid:0] Instruction is: addi a0, a0, -362 203000: system.cpu.fetch: [tid:0] Fetch queue entry created (2/32). 203000: global: Requesting bytes 0x6582e965 from address 0x104bc 203000: global: Decoding instruction 0x00006582 at address 0x104be 203000: global: DynInst: [sn:18] Instruction created. Instcount for system.cpu = 12 203000: system.cpu.fetch: [tid:0] Instruction PC 0x104be (0) created [sn:18]. 203000: system.cpu.fetch: [tid:0] Instruction is: c_ldsp a1, 0(sp) 203000: system.cpu.fetch: [tid:0] Fetch queue entry created (3/32). 203000: system.cpu.fetch: Branch detected with PC = (0x104be=>0x104c0).(0=>1) 203000: system.cpu.fetch: [tid:0] Done fetching, predicted branch instruction encountered. The instruction c.ldsp a1,0(sp), which is an instruction that reads data from memory, is detected as a branch (highlighted text). This behavior is negatively affecting the average issue rate from the fetch unit. Is that right? Is there some hardware limitation preventing that more than one memory instruction (load or store) can be fetched at a single cycle by the fetch unit? I don't understand the reason why two memory instructions could not be fetched in the same cycle. I am currently using the gem5 20.1.0.2 Risc-V ISA and se.py as the configuration file. This print that I showed before was obtained using O3CPUAll debug flag. Any help would be appreciated. ---------------------------------------------------------------------------------------------------------------------------------------------- Francisco Carlos Silva Junior Phd Student at University of Brasilia
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