Hi all, I have some questions related to TLB implementation in gem5. Gem5 seems to have implemented separate TLB for instruction and data paths, but I see that it has only one level. Real systems seems to have 2 levels of TLB, which I think is missing in gem5. Also, I see that TLB is not set associative as it is implemented in a trie and I assume that it is fully associative. But real processors like skylake have set associative TLB caches ( https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)) I see that the TLB implementation is very simple and I am wondering if there are any special reasons for keeping TLBs so simple. Thank you in advance. -- Regards, Krishnan.
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