[gem5-users] Dynamically Inserting lfence in decode

[George Klimiashvili via gem5-users]

Hello everyone,

Hope all is well. I am working on implementing an fsm that would dynamically 
insert lfence instruction during one of the state transitions. I’ve implemented 
the fsm in the decode stage.

Here is how I tried inserting the lfence instruction inside the decodeInsts 
function of o3 core:

// Line 680 in decode_impl.hh
// My code begins
DynInstPtr lfence_inst = buildInst(tid, StaticInst::nopStaticInstPtr,
                                    NULL, inst->pcState(), inst->pcState(), 
false);
lfence_inst->staticInst->setFlag(IsReadBarrier);
lfence_inst->staticInst->setFlag(IsSerializeAfter);

toRename->insts[toRenameIndex] = lfence_inst;

++(toRename->size);
++toRenameIndex;
// My code ends

where buildInst function is similar to buildInst function defined in 
fetch_impl.hh:

template<class Impl>
typename Impl::DynInstPtr
DefaultDecode<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
                              StaticInstPtr curMacroop, TheISA::PCState thisPC,
                              TheISA::PCState nextPC, bool trace)
{
    // Get a sequence number.
    InstSeqNum seq = cpu->getAndIncrementInstSeq();

    // Create a new DynInst from the instruction fetched.
    DynInstPtr instruction =
        new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu);
    instruction->setTid(tid);

    instruction->setThreadState(cpu->thread[tid]);

    DPRINTF(Decode, "[tid:%i] Instruction PC %#x (%d) created "
            "[sn:%lli].\n", tid, thisPC.instAddr(),
            thisPC.microPC(), seq);

    DPRINTF(Decode, "[tid:%i] Instruction is: %s\n", tid,
            instruction->staticInst->
            disassemble(thisPC.instAddr()));

#if TRACING_ON
    if (trace) {
        instruction->traceData =
            cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
                    instruction->staticInst, thisPC, curMacroop);
    }
#else
    instruction->traceData = NULL;
#endif

    // Add instruction to the CPU's list of instructions.
    instruction->setInstListIt(cpu->addInst(instruction));

    return instruction;
}

When I try running it on a test program, I get segmentation fault:

info: Entering event queue @ 0.  Starting simulation...
gem5 has encountered a segmentation fault!

While there are obvious problems with this code (this and next PC being same 
and wrong), I was wondering if you could give some directions. Do I have the 
right idea? Or should I be doing something completely different?

Any type of feedback would be much appreciated.

Best regards,
George Klimiashvili


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