Hi, We have been trying to make Ruby to work with X86 multi-core system attaching an NIC.
My understanding is that in Ruby, IO accesses don't go through the cache coherency protocol. And we have seen some malfunction during the simulation. (i.e NIC performed DMAwrite to memory but CPU was seeing the staled data from the cache) In the classical memory model, an IO cache is added between the IOBus and MemBus to give the IO device a coherent view of the memory, I wonder is there also a workaround for Ruby to make coherent IO accesses? Thank in advance, Hejing
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