Hi Deepak, I guess, if you care about more accurate implementation you might have to add new instruction in the ISA or maybe adding a new gem5 pseudo instruction will be easier. Also, according to my understanding, you might be able to use the cache invalidation/flushing related functionality in gem5 that exists there to implement similar instructions of other ISAs. For example, for reference, you can search for flush/invalidate in these files:
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/mem/cache/cache.cc https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/mem/cache/cache_blk.hh Specially, you might be able to use the invalidate function from cache block to invalidate (or effectively flush) a cache line (depending on what details you care about). -Ayaz On Wed, Jun 16, 2021 at 5:19 AM Deepak Mohan via gem5-users < gem5-users@gem5.org> wrote: > ---------- Forwarded message --------- > From: Deepak Mohan <usr...@gmail.com> > Date: Wed, Jun 16, 2021 at 5:16 PM > Subject: Re: [gem5-users] Making an address range uncacheable RISCV FS. > To: Ayaz Akram <yazak...@ucdavis.edu> > > > Hi Ayaz, > Thank you, it looks great, I was working with a previous version of > gem5. I would like to know one more thing, is there any way to flush a > cache line in gem5 RISCV, from my initial research I found that RISCV > currently doesn't provide any instruction to achieve this, is there > any way to achieve this in gem5 currently or should I try to add a new > instruction for this. > > Thank you, Regards > Deepak Mohan > > On Wed, Jun 16, 2021 at 2:20 AM Ayaz Akram <yazak...@ucdavis.edu> wrote: > > > > Hi Deepak, > > > > RISC-V PMA is supported in gem5. You can have a look at the source here: > https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/riscv/PMAChecker.py > > > > Also, here is an example of how this can be used in the gem5 config > script: > > > > > https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-fs/configs-riscv-fs/system/system.py#214 > > > > -Ayaz > > > > On Tue, Jun 15, 2021 at 1:23 PM Deepak Mohan via gem5-users < > gem5-users@gem5.org> wrote: > >> > >> Hi, > >> I was writing an OS that can run on RISC-V FS mode in gem5. I want > >> to make certain address ranges uncacheable (for some memory mapped > >> devices). RISCV page table entries doesn't provide any flags to > >> achieve this. The proper way to do this in RISCV seems to be using PMA > >> (Physical Memory Attributes), but I couldn't find any implementations > >> of PMA in gem5. Is PMA implemented for RISCV in gem5 ? Is this the > >> right approach to solve this problem ? Can anybody give me any ideas > >> to solve this problem ? It will be great if anyone can provide some > >> ideas. > >> > >> Thanks, > >> Deepak Mohan > >> _______________________________________________ > >> gem5-users mailing list -- gem5-users@gem5.org > >> To unsubscribe send an email to gem5-users-le...@gem5.org > >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >
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