Hello I have been studying the CHI documentation and the configs/ruby/CHI.py file.
Both the code and the documentation mention about 1) Map each CPU in the system to an RNF with private and split L1 caches 2) Add a private L2 cache to each RNF So what happens if the CPU model already has implemented L1/L2 caches (ie - if cpu type is O3_ARM_v7a_3)? Are the existing caches stripped out and CHI compliant caches added? Thanks in advance? JO
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