Hi Will, I am not exactly sure about what your final goal is. I am assuming that you want a coherent cacheable write issued by L1 (typically caused by a write back) to bypass L2 and directly hit L3. I am pretty confident saying that bypassing a single cache level in gem5's classic cache system is not possible. The fact that, by definition of a cache hierarchy, there is no port connections between L1 and L3 but only between L1 and L2 and between L2 and L3, is a first reason for this being impossible. An access is either cacheable and will hit as high as possible in the hierarchy, or non cacheable and will traverse the entire cache hierarchy to reach the targeted device.
However, if such behavior is really what you want, you could implement it yourself in at least two ways. You can either (1) add an extra port to make L1 able to communicate directly with L3 through the regular protocol or (2) flag requests targeted at L3 in such a way that L2 forwards them directly. I would probably go for (2) not to disturb the cache hierarchy structure too much. Anyway, both approaches will have subtle consequences on cache coherence which you must handle. To be specific, what happens if L2 has a valid cacheline and L1 wants to directly write this line to L3 for some reason? L2 will no longer be valid so L3 must snoop-invalidate it. But this is not the way a cache "hierarchy" usually works. If you really want to experiment with exotic caching and coherence mechanisms, you will likely be more comfortable using Ruby. Best, Gabriel _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
