Hi Andreas,

Could you provide us more information about the platform you are using?
More specifically

1) Are you using any configs/example/arm based script?
2) Which bus is connected to the device DMA port?

You need a cache between the device and the coherent bus. This is why we 
usually instantiate a IO cache
between the iobus and the membus [1]

Kind Regards

Giacomo

[1]: 
https://github.com/gem5/gem5/blob/stable/configs/example/arm/devices.py#L392


> -----Original Message-----
> From: diavastos--- via gem5-users <gem5-users@gem5.org>
> Sent: 13 September 2021 13:42
> To: gem5-users@gem5.org
> Cc: diavas...@gmail.com
> Subject: [gem5-users] Accelerator as PIO device writing back to main
> memory
>
> Hi all,
>
> I implemented an accelerator as a PIO device in the latest version of gem5
> and I am having issues with accessing the main memory for write operations.
> Reading from main memory works correctly.
>
> I used as an example an old entry "gem5-accel" that implements a Daxpy
> accelerator (as far as I saw even more recent implementations use a similar
> way to access main memory). My implementations for data transfer are
> more or less the same as the example but writing back to main memory
> doesn't work and I get the following runtime error:
>
> gem5.opt: build/ARM/mem/snoop_filter.cc:224:
> std::pair<std::vector<QueuedResponsePort*>, Cycles>
> SnoopFilter::lookupSnoop(const Packet*): Assertion `cpkt->isWriteback() ||
> cpkt->req->isUncacheable() || (cpkt->isInvalidate() == cpkt-
> >needsWritable()) || cpkt->req->isCacheMaintenance()' failed.
>
> If I manually change the Packet type (just to avoid this error) to
> MemCmd::WritebackDirty instead of the standard MemCmd::WriteReq, the
> simulation continues with no error but the data are not actually written back
> to main memory.
>
> Any ideas from anyone would be greatly appreciated! Or if there are other
> examples I can follow to do the implementation
>
> Many thanks,
> andreas
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