Hi Soramichi, We recently added the concatenation change to distinguish TLB entries of different processes to make SMT work. You can check more details here:
https://gem5.atlassian.net/browse/GEM5-332 I am not sure what the behavior should be for global pages. From some discussion here: https://stackoverflow.com/questions/41986862/x86-64-page-table-global-bit, it seems we should have the option to flag a TLB entry as a global entry. -Ayaz On Sat, Jan 28, 2023 at 1:04 AM Soramichi Akiyama via gem5-users < gem5-users@gem5.org> wrote: > Hello, > > I am trying something related to the global bit of a TLB entry and found > that the gem5 code might have inconsistency with the Intel manual. > > The Intel manual says that > "a logical processor may use a global TLB entry to translate a linear > address, > even if the TLB entry is associated with a PCID different from the current > PCID". > > However in TLB::translate(), gem5 concatenates the PCID to the vaddr when > CR4.pcide > is true and lookup the trie containing the TLB entries using [vaddr + PCID] > without considering the global bits of the entries. > > Is the gem5 behavior a bug, or is it a subset of allowed behaviors? > I guess it depends on what the word "may" in the manual means, but not > quite sure. > > Best regards, > > Soramichi Akiyama > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org >
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