On 6/10/2023 11:12 AM, Vincent Abraham via gem5-users wrote:
Hi everyone,
I'm trying to model additional latencies in the main memory while performing write/read operations.
Could anyone tell me how I could go about doing it?
Of course the dram module has a gazillion timing and energy parameters that
you can simply look up in your config.ini file, if that's what you mean.
But I suspect you want to know something like the distribution of access
times. You can see comm_monitor for statistics examples (and the memory
controller already has a lot as well), but it might go roughly like this.
First, set up a map in the controller module along these lines:
hash_map<PacketPtr, Tick> arrivalTime;
When a packet arrives at the controller, put it into the map like this:
arrivalTime.emplace(pkt, curTick());
Later, when the packet has finished processing, you can find out how long it
took by code like this:
auto it = arrivalTime.find(pkt);
assert(it != arrivalTime.end); // it really should be there
Tick arrival = it->second;
Tick latency = curTick() - arrival;
arrivalTime.erase(it);
The other part is recording statistics. To get a histogram over all packets,
declare a stat like this as a member of the memory controller's class:
Stats::Histogram pktLatencies;
In the controller module's regStats function, add this:
pktLatencies
.init(20) // or whatever number of buckets you want
.name(name() + ".pkt_latencies")
.desc("Histogram of packet latencies")
.flags(cdf | dist | nozero); // I like cdf, but pdf can be good too
Of course you don't have to use a histogram, and you don't have to use just
one. For example, you could have one for reads and one for writes, and enter
packets conditionalized on isRead() and isWrite().
The one piece I did not mention yet is adding a sample to the histogram. When
a packet finishes and you know its latency, just do:
arrivalTimes.sample(latency);
The magic of stats will do the rest.
Cheers - Eliot Moss
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