On 2/14/2024 11:19 AM, reverent.green--- via gem5-users wrote:
Hello everyone,
can someone give me a hint, where exactly in the code the architectural state of (load) instructions is getting set and
becomes visible? I tried to trace instructions during the execution via log outputs, but got a bit lost during the IEW
stage.
I know, that instructions, which depend on specific registers will wait until the register is marked ready from an
earlier usage. (https://github.com/gem5/gem5/blob/stable/src/cpu/o3/regfile.hh#L273)
But is this already equivalent to the architectural state?
And how is this handled during a wrong speculative execution because of the
following rollback/squashing?
Kind regards
Robin
A typical out-of-order processor does register renaming, so there are
generally *many* more physical registers than architectural ones, and the
hardware maintains a dynamic mapping. If necessary, the architectural state
can be constructed, but generally would not be unless you're switching threads
or something. While IEW may update the registers (I believe), it is the
commit stage that makes the change "permanent".
Does that help?
Eliot Moss
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