Hello.
Is there a way, to change cacheline size for different level of cache ?
Example: L1 cacheline size is 64 byte and L2 is 128 bytes ?
If there is not a direct way (changing some parameter from python), what will
be the issues with building this ?
Things I know:
1. fetchbuffer size has to be equal or less than cacheline size, otherwise
panic happens in gem5 (although I dont know why, and would like to know).
2. In src/mem/cache/cache.cc, the constructor for cache::basecache() is called
with p.system->cacheLineSize(). I am guessing changing this to user defined
value will let me get a cache with whatever cacheline I want. However, I saw in
cache.cc, Cache::satisfyRequest():
// determine if this read is from a (coherent) cache or not
if (pkt->fromCache()) {
assert(pkt->getSize() == blkSize);
>From the comment, it looks like this is for a request either from another
>cache from same level (2 L1 cache in 2 processor), or it can be from L1 to L2.
The assertion is making me think, separate cacheline size will not work here.
_______________________________________________
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
