[gem5-users] Why there is miss prediction of non-control instructions

[Atul Rahman via gem5-users]

Hello,
In function checkSignalsAndUpdate(ThreadID tid) in src/cpu/o3/fetch.cc file, it 
seems miss prediction can still happen from commit and decode even if 
mispredictInst->isControl() is false.
```
// Check squash signals from commit.
    if (fromCommit->commitInfo[tid].squash) {

        DPRINTF(Fetch, "[tid:%i] Squashing instructions due to squash "
                "from commit.\n",tid);
        // In any case, squash.
        squash(*fromCommit->commitInfo[tid].pc,
               fromCommit->commitInfo[tid].doneSeqNum,
               fromCommit->commitInfo[tid].squashInst, tid);

        // If it was a branch mispredict on a control instruction, update the
        // branch predictor with that instruction, otherwise just kill the
        // invalid state we generated in after sequence number
        if (fromCommit->commitInfo[tid].mispredictInst &&
            fromCommit->commitInfo[tid].mispredictInst->isControl()) {
            branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
                    *fromCommit->commitInfo[tid].pc,
                    fromCommit->commitInfo[tid].branchTaken, tid);
        } **else {
            branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
                              tid);
        }**

        return true;
    }
```
Can someone please explain when would this else condition be true? How can 
there be miss prediction of non-control instructions?




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