Hi all, I am trying to study the performance impact of off-chip bandwidth contention on CMP. Currently, I only use the number of L2 misses, because the L2 miss goes off-chip. But I have no clear idea about how to relate the off-chip bandwidth limitations with L2 misses. Are memdepunit.memDep.conflictingLoads and memdepunit.memDep.conflictingStores good metrics to use?
Thanks Meng-Ju _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
