I think the O3 cpu loads a whole cache line of instructions at a time, but perhaps I'm mistaken. EIther way the CPU and l1 cache are so closely integrated in a actual design that I don't know how realistic a generic bus power model would be for that transfer.
Ali On Aug 28, 2008, at 9:10 PM, Steve Reinhardt wrote: > You're correct that in the standard configs there's no bus between > the L1 and the CPU. However the CPU normally never loads or stores > more than 64 bits at a time so it's generally not an issue. If you > added some instruction that loaded entire cache blocks, then you > might have to worry about that. > > Steve > > On Thu, Aug 28, 2008 at 4:09 PM, richard strong <[EMAIL PROTECTED]> > wrote: > I see that for the l2bus, but the l1cache does not have such a > width. It > appears that the entire cache line (packet) is sent at once to the > cpu. > > -Rick > > nathan binkert wrote: > > All busses have a width parameter. Check out config.ini. > > > > Nate > > > > On Wed, Aug 27, 2008 at 3:00 PM, richard strong <[EMAIL PROTECTED]> > wrote: > > > >> Hi, > >> > >> I am trying to determine the bus width of the bus connected to a > cache. > >> Is this just the address range of the port connected to the cache? > >> > >> -Rick > >> > >> _______________________________________________ > >> m5-users mailing list > >> [email protected] > >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > >> > >> > >> > > _______________________________________________ > > m5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
