Hi, I'm trying to simulate a system with a Three Level Cache configuration
L1 (one per core), L2 shared and L3 shared. This is my code for the cache:
system.l2 = L2Cache(size='2MB')
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
system.l3 = L2Cache(size='32MB')
system.l3.cpu_side = system.tol2bus.port
system.l3.mem_side = system.membus.port
I define a tol2bus and I connect to them the L2 cpu side and the L3 cpu side
and after I connect the L2 mem side and the L3 mem side to the membus.port,
and this is the output that I get when I'm trying to simulate the system:
fatal: system.tol2bus has two ports with same range:
system.l3-cpu_side_port
system.l2-cpu_side_port
I imagine that the error is because I'm connecting L2 and L3 to the same
bus, but if I don't do this in this way how can I design my system?, Do I
need to define another bus for the L3 cache and after connect that bus with
the bus of the L2 Cache?.
Thank you.
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