Hi everyone, I'm trying to implement SMARTS-like functionality in the Alpha SE version of m5. So far I have managed to get the simulator to switch between the AtomicSimpleCPU and DerivO3CPU and back again repeatedly. I've also implemented functionality to do the switching after a certain number of instructions (instead of cycles).
However, when I switch cpus, I set the new CPU to use the warmed caches from the old cpu. The same doesn't happen for the itb and dtb. In fact, from looking at the code I think that 2 different instances of these get created, one for each cpu. So, how easy would it be to implement this and where would I start? Could I do this in cpu/BaseCPU.py, cpu/base.cc, cpu/base.hh only or do I need to consider other places too? Thanks for your help Tim -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
