It's pretty hard to know what's going on from such basic information. There is something very strange if the memInhibit signal is being asserted on an uncached request though. The only real way to debug something like this is to look at the request that's causing the assertion failure, probably stepping through the request in gdb to figure out which cache is setting memInhibit, and maybe even dumping some memory traces up to that point to see how you got in that state. (If you turn on tracing a few million ticks before, and then grep for transactions to the relevant block address before redirecting to a file, the traces don't get so large.)
Steve On Wed, Aug 12, 2009 at 7:00 PM, Shoaib Akram<[email protected]> wrote: > I have a 3-level cache hierarchy, full system mode. Everything is fine with > monolithic shared bus. When I enhance the bus to make an interconnect as > shown in attached pdf file, the l3 cache fails the following assertion: > > if (pkt->memInhibitAsserted()) { > assert(!pkt->req->isUncacheable()); > > The fact is that in attached figure the path of requests is same, snooping is > atomic, and the shown bridges are only adding a certain delay to requests. I > don't see the reason very clear, any take on this is appreciated. > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
