Hello, I was wondering, is there a way to get a trace of only the memory operations (loads and stores) that miss in the L2 cache (i.e those that need to access main memory)? I'm currently using the AtomicSimple CPU model.
Thanks, Felix _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
