> I figured out that there are 4 "stages" each instruction needs to pass. > Should be 5 stages right? FDXMW... there is light documentation on m5sim.orgthat you might want to check out.
> Each stage calls the resources of the in-order core. > I tried to modify the "stageWidth"-parameter in the hope that more > buffer slots would be available at each stage but unfortunately nothing > changed. Unfortunately, the stageWidth param in the python interface doesnt translate to the inorder design just yet. We plan to get everything fully configurable thorugh the Python command line interface in due time. For now, you want to edit the "StageWidth" constant in file src/cpu/inorder/pipeline_traits.hh and recompile. That probably will do the trick. -- - Korey
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