Thank you for your reply, Korey. As you said, different CPUs are executed in their own address space, thus they are mutual exclusive even when they are executed on the same code. But how about when they communication with the same I/O device. Say multiple CPU write something to the same I/O devie in arbitrate order, and there seems to be no guarantee for the order that the I/O device recevies and processes these requests. If every request contains several write or read in the CPU, how can then be atomic? Thank you very much!
2010/2/11, Korey Sewell <[email protected]>: > > Unless you specifically setup some type of multithreaded execution, each > thread/each CPU will default be treated as it's own process, thus even if > they are executed on the same code, they will be in a different address > space. Consequently, like Gabe said, they will be mutually exclusive. > > 2010/2/11 Veydan Wu <[email protected]> > > Thank you for your reply, Gabe. But how does M5 switch among multiple >> simulated CPUs? There must be some points where it does such as change. Is >> there any possibility that these CPUs' execution will general race >> condition? Thank you! >> >> 2010/2/11 Gabe Black <[email protected]> >> >> M5 is single threaded right now, so they should all be mutually >>> exclusive by default. >>> >>> Gabe >>> >>> Veydan Wu wrote: >>> > Hi, is there any lock or something else I can use in order to achieve >>> > mutual exclusive in M5? For example, I want to implement a piece of >>> > code in the CPU model, such as in the postExecute() function. There >>> > are 4 cpu in my simulation, so every cpu will execution this extra >>> > code without any order guarantee. How can I make them mutual >>> > exclusive? Should I implement a lock by myself or is there anything I >>> > can use in M5. Thank you very much! >>> >>> > >>> ------------------------------------------------------------------------ >>> > >>> > _______________________________________________ >>> > m5-users mailing list >>> > [email protected] >>> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >>> _______________________________________________ >>> m5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >> >> >> >> -- >> 吴为丹 >> 中科院计算所 微处理器中心0853 >> 北京海淀区科学院南路6号 100190 >> (86-10)6260-0853 (86-10)8268-3196 >> (86)138-112-10636 >> [email protected] >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > > > -- > - Korey > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- 吴为丹 中科院计算所 微处理器中心0853 北京海淀区科学院南路6号 100190 (86-10)6260-0853 (86-10)8268-3196 (86)138-112-10636 [email protected]
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