Lisa is right that AverageStat is the best answer to your specific problem.
If you really did need to do something on every CPU tick in the cache though, I would recommend just adding a tick() method to the cache and an event to call it at the same frequency as the CPU rather than trying to indirectly do it via the CPU's tick function. Steve On Wed, Jul 14, 2010 at 1:57 PM, Lisa Hsu <[email protected]> wrote: > Ah, in this case, another possibility is to use the AverageStat statistics > type. Check out the description on m5sim.org, but basically, you wouldn't > need to do anything based on CPUs...increment and decrement the stat value > whenever something changes, and in the background it will keep track of > average over cycles in the simulation. That will probably simplify things a > lot for you. > Lisa > > On Wed, Jul 14, 2010 at 1:49 PM, Lide Duan <[email protected]> wrote: >> >> Hi Lisa, >> >> Thanks for your reply. Yes, this cache function should be called every CPU >> tick. What it does is very simple: just collect some cache information (e.g. >> how many blocks in Modified state, etc.) in current cycle, and at the end of >> simulation this accumulated counter will be divided by numCycles to get an >> average number. I would like to implement it in every cache object, >> including both private and shared ones. >> >> Actually I was able to figure out a way to possibly get to the cache >> object in CPU. E.g. in cpu.cc, in order to access L1 instruction cache, we >> can use: >> getPort("icache_port",0)->getPeer()->myCache()->someCacheFunc() >> However, the problem with the above line is that getPeer() only returns >> Port*, while myCache is a function of CpuSidePort which is defined in Class >> Cache (in mem/cache/cache.hh). How can I cast Port* to its subclass >> CpuSidePort*, especially when the subclass is defined in a template class >> (i.e. Cache)? >> >> Or perhaps what I am trying to hack here is completely wrong/infeasible? >> >> Lide >> >> >> On Wed, Jul 14, 2010 at 12:11 PM, Lisa Hsu <[email protected]> wrote: >>> >>> Hi Lide, >>> There isn't a direct way to access the caches from the CPU right >>> now...this is a design decision to keep M5 modular - all the CPU knows is >>> what is attached to its ports, that way you can have completely arbitrary >>> hierarchies and topologies without any dependencies in the CPU code as to >>> what the hierarchy looks like. >>> You'd have to hack something in...but it would definitely be a hack. If >>> you had a few more specifics about what you were trying to do, I or someone >>> could provide slightly more suggestions. Like, do you want this to happen >>> for every cache in the hierarchy or just a specific level? Are the caches >>> you want this to happen to shared? If so, would you want this function to >>> get called N times per cycles for N cpu tick calls, or just once across all >>> the CPUs? >>> Lisa >>> >>> On Wed, Jul 14, 2010 at 8:36 AM, Lide Duan <[email protected]> wrote: >>>> >>>> Hi, >>>> >>>> Probably this is a silly question: how can I access the instantiated >>>> cache objects in the cpu object? I understand that the CPU sends requests >>>> to >>>> I/D cache ports which further connect to the caches. But what I am trying >>>> to >>>> do is to call a cache object function directly in the CPU, is it possible? >>>> More specifically, I need to collect some cache statistics every cycle, so >>>> I >>>> implemented a function (in Cache class) to do it, and need to call this >>>> function in CPU tick(). Then I came up with the problem that I couldn't >>>> access the cache objects in cpu. I found that the cache object is created >>>> in >>>> BUILD_CACHE in mem/cache/builder.cc, but where does it go after that? >>>> >>>> Anybody has some idea about this? Thank you very much! >>>> >>>> Lide >>>> >>>> _______________________________________________ >>>> m5-users mailing list >>>> [email protected] >>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >>> >>> _______________________________________________ >>> m5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
