You're on the right track... off the top of my head: M = Valid, Writable, Dirty O = Valid, !Writable, Dirty E = Valid, Writable, !Dirty S = Valid, !Writable, !Dirty I = !Valid
Note that Readable is only false for Valid blocks in transient states. Steve On Thu, Jul 15, 2010 at 9:50 AM, Lide Duan <[email protected]> wrote: > Hi, > > I read through the cache source code though haven't caught every detail of > it. I think the block coherence state is reflected in CacheBlk::status which > contains six bits indicating Valid, Writable, Readable, Dirty, Referenced, > and Prefetched, respectively. The status bits will be set/removed > accordingly with respect to different cache operations. Then my question > becomes: What bit(s) in block status should be set when this block is in > different MOESI states? > > For example, I guess the Modified state should be Valid, Writable, Readable, > and Dirty, while Shared state should not be Writable. Is there a clear > relationship between the status bits and each of the five coherence states? > > Any ideas? Thank you! > > Lide > > On Tue, Jul 13, 2010 at 4:05 PM, Lide Duan <[email protected]> wrote: >> >> Hi, >> >> By reading the documents and previous mail archive, I know that MOESI >> coherence protocol has been hardwired into current m5-stable release >> (right?). Where is the coherence state recorded exactly? Currently, I am >> trying to collect statistics regarding different coherence states (e.g. how >> many blocks are in Shared state each cycle, etc). Can anybody point me a >> fast way to do it? >> >> Thanks, >> Lide > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
