That looks to me like it should work.
On Thu, Jul 15, 2010 at 9:47 AM, Zhe Wang <[email protected]> wrote: > Hi Steve > This is last part of my config file: > se.py: > for i in xrange(np): > process = LiveProcess() > process.executable = benchmarks[i][0] > process.cmd = benchmarks[i][0] > > # input file (as option) > if benchmarks[i][1] != "": > process.cmd = [benchmarks[i][0],benchmarks[i][1]] > > # output file > if benchmarks[i][2] != "": > process.output = benchmarks[i][2] > > # assign the benchmark to workload > system.cpu[i].workload = process > > # assign split L1 cache to each core > if options.caches: > system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), > L1Cache(size = '64kB')) > > # if L2 cache exits, connect mem port to l2 cache > if options.l2cache: > system.cpu[i].connectMemPorts(system.tol2bus) > else: > system.cpu[i].connectMemPorts(system.membus) > > if options.fastmem: > system.cpu[i].physmem_port = system.physmem.port > > system.cpu[i].clock = '2GHz' > system.cpu[i].fetchWidth=2 > system.cpu[i].decodeWidth=2 > system.cpu[i].renameWidth=2 > system.cpu[i].dispatchWidth=2 > system.cpu[i].issueWidth=2 > system.cpu[i].wbWidth=2 > system.cpu[i].commitWidth=2 > system.cpu[i].squashWidth=2 > # system.cpu[i].max_insts_all_threads = 100000000 > > # ===================================== > # Run simulation > # ===================================== > root = Root( system = system ) > #Simulation.run(options, root, system, FutureClass) > > # Not much point in this being higher than the L1 latency > # m5.ticks.setGlobalFrequency('1ns') > > # instantiate configuration > m5.instantiate(root) > > #======================================= > > > > Did you see anything wrong? > > Thanks > > Zhe > > On 7/15/2010 11:14 AM, Steve Reinhardt wrote: >> >> It should work in the config file as long as you do it after the >> system is constructed but before you call instantiate. >> >> On Thu, Jul 15, 2010 at 7:43 AM, Zhe Wang<[email protected]> wrote: >> >>> >>> Hi Jie >>> Thanks for replying. >>> I clean up all the previous build and recompile M5, it works. >>> >>> I tried write "system.cpu[i].issueWidth=2" in the se.py file, but >>> this >>> one doesn't work. It still give me issue_width = 8, any ideas how to do >>> it >>> in configuration file? >>> >>> Thanks >>> >>> Zhe >>> >>> >>> >>> On 7/14/2010 5:17 PM, Jie Meng wrote: >>> >>>> >>>> Hi Zhe, >>>> >>>> Did you recompile M5 to make the change work? If m5 is recompiled with >>>> the >>>> the change in O3CPU.py, you should see it in the new config.ini file. >>>> >>>> You could also change the "fetch_width" or "issue_width" in your se.py >>>> or >>>> fs.py configuration files. For example, "system.cpu[i].issueWidth=2; ... >>>> ". >>>> >>>> Hope this would help! >>>> >>>> Best, >>>> Jie >>>> >>>> >>>> On Jul 14, 2010, at 3:34 PM, Zhe Wang wrote: >>>> >>>> >>>> >>>>> >>>>> Hi >>>>> I am trying to use O3 cpu and change the fetch_width and >>>>> issue_width >>>>> into a smaller one ( default is 8). I found the default value is set in >>>>> src/cpu/o3/O3CPU.py. But after I change it in the O3CPU.py file, the >>>>> output >>>>> file config.ini still give me "fetch_width=8". Could someone tell how >>>>> to >>>>> change it? >>>>> >>>>> Thanks >>>>> >>>>> Zhe >>>>> _______________________________________________ >>>>> m5-users mailing list >>>>> [email protected] >>>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>>>> >>>>> >>>> >>>> _______________________________________________ >>>> m5-users mailing list >>>> [email protected] >>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>>> >>>> >>>> >>> >>> _______________________________________________ >>> m5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >>> >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> >> > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
