Hi all,
we're two students that have to monitor memory traffic on the M5 Simulator,
using parsec benchmark as inputs. After many simulations we've encountered some
problems caused by the comprehension of output file stats.txt (detailed mode).
First question is why there are two simulations in that file? (we have found
two begin simulation-end simulation in the same file).
After this question we would know:
# cache L1 access (instruction cache, data cache);
# cache L2 access;
# TLB access;
# main memory access
We've found many interesting counter into stats.txt, but we're not sure that
they're what we are searching for. We think we could calculate this values in
such way:
# cache L1 access = system.cpu0.dcache.overall_accesses +
system.cpu0.icache.overall_accesses;
# cache L2 access = system.l2.demand_accesses;
# TLB access=system.cpu0.dtb.data_accesses + #system.cpu0.itb.data_accesses
# main memory access=MSHR access
Could everyone help us please?confirming our ideas or saying us where we have
mistaken?
Thanks a lot,
Alessandro and Giorgio
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