Thanks for your reply.
I understand that it is not officially supported. But from the source
code and runtime dump info, my understanding is that each step
throughout the memory access process, differences in cache line size
seem have been considered. For example, the data size stored in the
packets are corresponded to the line sizes at each cache level. Maybe, I
guess, it's just about the size but the actual data (e.g. to be written
back to L2 from L1) is not correct? The only place I can think of which
may corrupt the data due to line size differences is when dirty blocks
are written back from d-cache to L2 cache. Am I on the right track?
Weixun
On 7/21/2010 2:21 PM, Gabe Black wrote:
Weixun Wang wrote:
Hi all,
I'm trying to get M5 work with different line sizes in different
caches (i-cache, d-cache and l2). I found that M5 works fine with a
lot of scenarios where different caches have different line sizes
among cores (I verified the simulated apps' outputs). However, when it
comes to some other cases, especially when the L2 cache size is small
(e.g. 32kB), I got errors "Tried to access/execute unmapped address
XXX" from ItbPageFault::invoke() and NDtbMissFault::invoke().
I made M5 dump out messages throughout the memory access process
during simulation. I found that the error is caused by an invalid
virtual address of PC or data address. For example, in the read()
function of TimingSimpleCPU, (system.cpu TimingSimpleCPU::read() addr
= 7776240), the passed in parameter addr (which is the virtual
address) got the value "7776240", which is obviously an invalid
virtual address since in that case normal load/store has the vaddr of
sth like "4832631768". Therefore, the next step, which is calling the
TLB to translate the address, report such an error after looking up
the page table.
There is no error if the line sizes are the same. So I suppose the
error comes from line size differences. But I went through the M5
source code and found that actually memory access has taken the line
size differences among cache levels into consideration by
differentiating "size" stored in Request/Packet and the block size in
each cache. Block filling functions are also written in a right
manner. Moreover, the error comes from a bad virtual address in the
first place, which indeed has nothing to do with cache accesses. I'm
confused...
Any help will be appreciated!
Thanks!
Using different line sizes isn't supported, and it isn't surprising it
doesn't entirely work. It's likely the different sizes corrupted the
virtual address as it was brought in from memory, or corrupted a value
used to compute it. This segfault in the simulated program is probably a
symptom of a problem that happened earlier.
Gabe
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Best Regards,
Wang, Weixun
Department of Computer& Information Science& Engineering
Gator College of Engineering
University of Florida
Gainesville, FL 32611
http://www.cise.ufl.edu/~wewang
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