"Easy" is in the eye of the beholder, but it is a change that only
involves the python config script.

Steve

On Thu, Jul 22, 2010 at 9:56 AM, Eberle <[email protected]> wrote:
> Is there an easy way to configure the system like that (1 icache only)?
> (editing the python script?)
>
> --
> Eberle.
>
>
> On Wed, Jul 21, 2010 at 6:43 PM, Steve Reinhardt <[email protected]> wrote:
>>
>> That would probably work.  Thanks for cluing me in... hadn't thought
>> about verification applications.
>>
>> Steve
>>
>> On Wed, Jul 21, 2010 at 12:48 PM, Eberle <[email protected]> wrote:
>> > What about using only an icache and no dcache?
>> > We're experimenting with a new verification technique and want to
>> > observe
>> > the behavior with and without caches.
>> >
>> > --
>> > Eberle.
>> >
>> >
>> > On Wed, Jul 21, 2010 at 2:37 PM, Steve Reinhardt <[email protected]>
>> > wrote:
>> >>
>> >> O3 can deadlock if it doesn't have independent I&D caches... if the
>> >> dcache blocks, the pipeline will continuously replay blocked loads,
>> >> which saturates the icache port and will prevent the blocked loads
>> >> from issuing if they don't have an independent path.
>> >>
>> >> (At least that's how I remember it... I'm not sure why we go all the
>> >> way back to fetch to replay the blocked loads, but it's something like
>> >> that.)
>> >>
>> >> We never bothered to deal with it because we couldn't think of a
>> >> reasonable scenario where anyone would want a detailed CPU model w/o a
>> >> reasonably detailed cache hierarchy too.  I'm curious what your
>> >> motivation is...
>> >>
>> >> Steve
>> >>
>> >> On Wed, Jul 21, 2010 at 10:06 AM, Eberle <[email protected]> wrote:
>> >> > Is there a way to use the O3 CPU without caches, only using the main
>> >> > memory?
>> >> >
>> >> > Thanks,
>> >> >
>> >> > --
>> >> > Eberle.
>> >> >
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