Hi All, For my research I want to disable parts of the last level cache. In my case L3. Specifically, I need to implement 3 different behaviors 1) "selective cache-ways", during execution disable a cache-way, 2) "cache decay", there is a counter for each cacheline and after a predetermined threshold of ticks without the cacheline being accessed the cacheline gets disabled, 3) "drowsy cache", periodically all cachelines are set in drowsy mode, the cachelines are reactivated on access, which means I there is an additional delay for reactivation for every cacheline being accessed while in drowsy mode. Was curious: - has there been any work along those lines on m5? - I have not dived into the cache code that deep. One concern based on the previous posts ( http://article.gmane.org/gmane.comp.emulators.m5.users/3824/match=gaurav) is how to deal with a series of writebacks, (e.g. when I disable a whole cache way with dirty entries) and the buffers get full. - Other issues that I will run into?
I am using a modified version of m5 from R. Strong that supports directory coherence caches among other goodies. Thanks ------------------------------------------------------------------- Kontorinis Vasileios Phd student, University of California San Diego http://cseweb.ucsd.edu/~vkontori/ [email protected] -------------------------------------------------------------------
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