Could you rerun that inside gdb (using m5.debug preferably) and get a backtrace? Basically, this is a bounds check during the process of mapping a register index from an instruction/simulated program perspective down to an actual storage location managed by the CPU. Something, possibly the switching logic, seems to be trying to use a bad index, and it would be helpful to know where the call is coming from and what it's trying to do.

Gabe

Quoting john <[email protected]>:

Hello,

I've been trying to get fast forwarding to work with SPARC_SE. However, I
get the following error:

...
switching cpus
Assertion failed: (reg < TotalInstIntRegs), function flattenIntIndex, file
build/SPARC_SE/arch/sparc/isa.hh, line 194.

This happens both with my own scripts and configs/example/se.py, so I doubt
its a script configuration problem.

Any ideas on what the problem is / how to go about fixing it? Since we're
switching CPUs of the same ISA the register files ought to be identical, are
they?

Thanks in advance,
John



_______________________________________________
m5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users

Reply via email to