Hello, All, I have some question about the code of cache and bus section:
1. I am not quite clear about the usage about function "timingAccess(PacketPtr pkt)" and "handleResponse(PacketPtr pkt)" in file cache_impl.hh. My understanding is if the event is triggered by instruction or data fetch instruction, it will lead to call timingAccess function. But if the event is triggered by cache miss, it will call handlerResponse instruction. I know I must miss something here, is somebody can explain this? 2. I run some benchmark and backtrace the cache and bus event, I got part of the backtrace like this: 31491500: system.membus: recvTiming: src 0 dst 1 ReadResp 0x129b00 31491500: system.l2: Handling response to 129b00 31491500: system.l2: Block for addr 129b00 being updated in Cache 31491500: system.l2: Block addr 129b00 moving from state 0 to 7 31491500: system.membus: The bus is now occupied from tick 31491500 to 31494000 31504000: system.tol2bus: recvTiming: src 0 dst 1 ReadResp 0x129b00 31504000: system.cpu.icache: Handling response to 129b00 31504000: system.cpu.icache: Block for addr 129b00 being updated in Cache 31504000: system.cpu.icache: Block addr 129b00 moving from state 0 to 5 31504000: system.tol2bus: The bus is now occupied from tick 31504000 to 31506000 31507500: system.cpu.icache: ReadReq 129b40 miss Here I do not understand how the bus works. My understanding is the bus should be occupied when the data transfered from memory to l2 cache. So the membus should be occupied before system.l2 handling the response. But why here 31491500: system.membus: The bus is now occupied from tick 31491500 to 31494000, it is occupied after the l2 update the cache. I really appreciate you reply. Thanks. zhe
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