Hello, all, I run benchmark 471.omnetpp using m5 simulator SE mode. The command like m5.fast -d omnetpp -n 1 -d --caches --l2cache --max-inst==2000000000. That is I am using single processor, detailed memory model, run 2 billion instructions, 32M L1 data cache and 2M L2 cache.
I got the cache statistic for benchmark 471.omnetpp : the l1 data cache miss is 8.4 per 1000 instructions, L2 cache miss is 0.3 per 1000 instructions. But When I run the 471.omnetpp benchmark on the real Intel core 2 machine with 6M L2 cache, the cache statistics I collected is the L1 data cache miss is 30 per 1000 instructions, the L2 cache miss is about 8 per 1000 instruction. So, It seems the cache miss data collected by m5 simulator is not correct. Does anybody have idea about this? Thanks Best zhe
_______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
