Hello,
I'm having some problems running with 4 cores and a Nehalem-like cache
in the latest few updates of m5. Previously the three-level cache
structure had worked fine. Specifically, the error I am getting is:
build/ALPHA_FS/mem/cache/cache_impl.hh:909: void
Cache<TagStore>::handleResponse(Packet*) [with TagStore = LRU]:
Assertion `target->pkt->cmd == MemCmd::StoreCondReq || target->pkt->cmd
== MemCmd::StoreCondFailReq' failed.
I have added this to Options.py:
parser.add_option("--l3cache", action="store_true")
I have also updated Caches.py and CacheConfig.py and they are attached.
I updated the kernel to a newer rev according to the directions on the
web page.
(gdb) print *target
$2 = {recvTime = 2238099124338, readyTime = 2238099127776, order = 643,
pkt = 0x5a66ea0, source = 0, markedPending = true}
(gdb) print *target->pkt
$4 = {<FastAlloc> = {_vptr.FastAlloc = 0xc4ce10, static Max_Alloc_Size =
512, static Log2_Alloc_Quantum = 3, static Alloc_Quantum = 8, static
Num_Buckets = 65,
static Num_Structs_Per_New = <optimized out>, static freeLists =
{0x0, 0x0, 0x0, 0x0, 0x0, 0x59e3108, 0x0, 0x5a5ce28, 0x0, 0x59df018,
0x5a0cad0, 0x233ec90, 0x5a08e80,
0x0 <repeats 22 times>, 0x5a01b00, 0x0 <repeats 29 times>}},
<Printable> = {_vptr.Printable = 0xc4ce38}, static PUBLIC_FLAGS =
<optimized out>,
static PRIVATE_FLAGS = <optimized out>, static COPY_FLAGS = 15,
static SHARED = 1, static EXPRESS_SNOOP = 2, static SUPPLY_EXCLUSIVE =
4, static MEM_INHIBIT = 8, static VALID_ADDR = 256,
static VALID_SIZE = 512, static VALID_SRC = 1024, static VALID_DST =
2048, static STATIC_DATA = 4096, static DYNAMIC_DATA = 8192, static
ARRAY_DATA = 16384, flags = {_flags = 28416},
cmd = {static commandInfo = 0x11d1480, cmd =
MemCmd::SCUpgradeFailReq}, req = 0x59dc650, data = 0x5a70d10
"\320N\250\005", addr = 17759616, size = 64, src = 1, dest = -1, origCmd = {
static commandInfo = 0x11d1480, cmd = MemCmd::InvalidCmd}, time =
2238099124338, finishTime = 2238099126000, firstWordTime =
2238099127000, static Broadcast = -1,
senderState = 0x25876b8}
It works fine with only the L2 cache, the problem is adding the L3
cache. Any ideas?
Joe
# Copyright (c) 2010 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Lisa Hsu
# Configure the M5 cache hierarchy config in one place
#
import m5
from m5.objects import *
from Caches import *
def config_cache(options, system):
if options.l3cache:
system.l3cache = L3Cache()
system.tol3bus = Bus()
system.l3cache.cpu_side = system.tol3bus.port
system.l3cache.mem_side = system.membus.port
system.l3cache.num_cpus = options.num_cpus
elif options.l2cache:
system.l2cache = L2Cache()
system.tol2bus = Bus()
system.l2cache.cpu_side = system.tol2bus.port
system.l2cache.mem_side = system.membus.port
system.l2cache.num_cpus = options.num_cpus
for i in xrange(options.num_cpus):
if options.l3cache:
system.cpu[i].addTwoLevelCacheHierarchy(L1Cache(), L1Cache(), L2Cache())
system.cpu[i].connectMemPorts(system.tol3bus)
elif options.l2cache:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(), L1Cache())
system.cpu[i].connectMemPorts(system.tol2bus)
return system
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Lisa Hsu
from m5.objects import *
class L1Cache(BaseCache):
size = '32kB'
assoc = 4
block_size = 64
latency = '.9375ns'
mshrs = 10
tgts_per_mshr = 5
class L2Cache(BaseCache):
size = '256kB'
assoc = 8
block_size = 64
latency = '3.4375ns'
mshrs = 20
tgts_per_mshr = 12
class L3Cache(BaseCache):
size = '16MB'
assoc = 16
block_size = 64
latency = '12.25ns'
mshrs = 32
tgts_per_mshr = 12
prefetch_policy = 'ghb'
prefetch_degree = 3
prefetcher_size = 256
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '10ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
forward_snoops = False
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