It looks like this is because Linux is making assumptions about the
size of the L1 cache based on the type of CPU it thinks it's running
on. The function that sets it up appears to be here:
http://lxr.linux.no/linux+*/arch/alpha/kernel/setup.c#L1335
Note that while L1 instruction and data caches are always (as far as I
see) hard coded, L2 is sometimes measured with the
external_cache_probe function. It also looks like that function is
doing some math I don't want to take the time to unravel, but that the
largest size cache it'll detect may be MAX_BCACHE_SIZE which is set to
16MB. This is for 2.6.35.7 (the most recent version used by default at
lxr.linux.no) so it might not match exactly with the kernel you have,
but I assume that code hasn't changed much over time.
This all means you shouldn't really worry about what /proc/cpuinfo
says since it's not an accurate representation (in this case) of what
the hardware actually looks like. If you really want to be sure the
caches are sized the way you want them to be and are behaving
properly, you could try running a benchmark like the lat_mem_rd
portion of the lmbench microbenchmark suite. That might be overkill,
though.
Gabe
Quoting Yu Licheng <[email protected]>:
Hello, I'm working on changing cache configuration.
I found in configs/common/CachesConfig.py, there are L1 and L2
caches size configurations.
And I changed L2 cache size to 8MB, L1 cache size to 128KB and 256KB
using following code:
system.l2 = L2Cache(size='8MB')
...
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '128kB'),
L1Cache(size = '256kB'))
When I boot ALPHA_FS in detailed mode with caches and l2cache flag,
I found in /proc/cpuinfo, the L2 cache size is recognized as 8MB,
but L1 cache stayed 64KB:
(following is from /proc/cpuinfo)
L1 Icache : 64K, 2-way, 64b line
L1 Dcache : 64K, 2-way, 64b line
L2 cache : 8192K, 1-way, 64b line
It seems the L1 cache size did not changed. And I also tried to
change assoc and block_size in configs/common/Caches.py,
but nothing changed in the guest Linux's /proc/cpuinfo.
The m5 source code change set is 7699:addb847910d2(Gabe Black
submitted at Oct 04 11:58:06 2010),
and the guest system is m5_system_2.0b3, which was downloaded from m5 site.
So how can i actually change the L1 cache? Or maybe it changed but
the guest system did not recognize it?
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