The detailed timing model as far as CPUs is O3, and it won't work with x86 right now. I have some patches that get it working with the regressions in X86_SE which will hopefully get into the repository before too long, but it won't work in X86_FS for various reasons. Even then the performance won't be accurate because partial register writes are being handled naively. X86 uses a lock flag so that it can do atomic read/modify/write sequences. Conceptually, a read with the lock flag set locks the memory, and then a store with the lock flag set unlocks it. This is implemented differently depending on how the memory system is set up (I don't know if it works in Ruby or timing mode) but it doesn't use LL/SC at all, as far as I remember. In atomic mode, the CPU handles everything by continuing to execute instructions until the read/modify/write sequence has happened in its entirety. Since memory accesses are atomic, the CPU knows nothing else can interrupt that instruction sequence other than a fault. The load also makes sure the store won't fault, so that shouldn't be a problem.
Gabe On 10/26/10 17:34, dibakar gope wrote: > Hi All, > > I am trying to run the timingCPU model for X86_FS. I could make it run > in atomic mode. But for the detailed timing model in X86_FS , I guess > that Ruby memory model will be used because of the different locking > mechanisms X86 uses rather than the regular M5 memory model. > So for the X86_FS to work, I was trying to find out the locking mutex > in Ruby. I found in the code of iew_impl.hh and rename_impl.hh that > alpha arch. in M5 is using LL/SC mutex somewhat. Somewhere I found in > the M5wiki, that X86 will use bus locking mechanisms. So I just wanted > to know :- > > (1) what are the h/w locking mechanisms X86 is likely to use? are > those h/w mutex alreday implemented in Ruby? what's the current status > of the h/w locks implementation in x86? > > (2) what's the code tree in Ruby memory model, I should try looking at > for the different h/w locks in X86? > > (3)Has Ruby been integrated for the detailed memory model in X86? > > Please let me know. Any help will be greatly appreciated. > > > Thanks, > -Dibakar Gope > Texas A&M university > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
