On 11/02/10 12:03, reena panda wrote: > Hi All, > > I am trying to collect memory traces of the PARSEC benchmarks using M5 > sim in the timing cpu model of ALPHA_FS mode. Basically, I am > interested in collecting the PC of the Data memory access > instructions, the virtual addresses of the data references and > corresponding physical addresses. > > Upon exploring, I found the following > a) The PageTable class is defined for only the SE mode and is hence, > not relevant in my case
Yes, the PageTable class is to allow M5 to fake page table management that would normally be done by the OS. It's needed in SE when there's no OS and not in FS when there is. > > b) All the possible data virtual address->physical address > translations for ALPHA_FS is being done in the functions defined in > src/arch/alpha/tlb.cc file. But It seems that even if a virtual > address doesn't hit in the TLB, the corresponding page table walk is > also done in the lookup function and the TLB updated simultaneously? > Is it correct? TLB misses in Alpha cause a fault, I'm pretty sure, and the simulated software does the lookup and updates the TLB. > > So, based on the above observation, I am trying to tap the PC, virtual > address and physical addresses of individual memory access > instructions in the DataTranslation::finish function (defined in > cpu/translation.hh) as follows: > if(fault == NoFault && (!req->isPrefetch())) > req->getPC(), req->getPaddr(),req->getVaddr() > > I just wanted to confirm if I am tapping the items at the right place? > Or am I missing something here? I think that would basically work, although it's hard to say for sure. You could look at the tracing infrastructure (look for traceData and the things that manipulate it) which might make what you're doing a little cleaner/easier. You can repurpose the object that traces instruction execution for when you use the Exec trace flag, or you can write your own replacement tracer and set the CPU to use it instead. Gabe _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
