Hi, I've been using M5's ARM frontend with the AtomicSimpleCPU model for a while and it mostly works for simple binaries. Trying out the O3CPU model, however, gives me :
FullO3CPU: Ticking main, FullO3CPU. 1322500: system.cpu: Thread 0: Deleting instructions from instruction list. 1322500: system.cpu: ROB is not empty, squashing insts not in ROB. m5.debug: build/ARM_SE/cpu/o3/bpred_unit_impl.hh:350: void BPredUnit<Impl>::squash(const InstSeqNum&, const ArmISA::PCState&, bool, ThreadID) [with Impl = O3CPUImpl, InstSeqNum = long unsigned int, ThreadID = short int]: Assertion `pred_hist.front().seqNum == squashed_sn' failed. Program aborted at cycle 1322500 Aborted Is this a known issue? I have no knowledge of M5 internals so I can't really make an educated guess as to what the problem could be. Has someone else stumbled across this too? Thanks. -- Jai Menon _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
